In-memory area-efficient signal streaming processor design for binary neural networks

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2017.8052874 ◽

2017 ◽

Cited By ~ 2

Author(s):

Haruyoshi Yonekawa ◽

Shimpei Sato ◽

Hiroki Nakahara ◽

Kota Ando ◽

Kodai Ueyoshi ◽

...

Keyword(s):

Neural Networks ◽

Processor Design ◽

Memory Area ◽

Area Efficient

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Energy and Area Efficient Tunnel FET-based Spiking Neural Networks

2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) ◽

10.1109/edtm.2018.8421527 ◽

2018 ◽

Cited By ~ 1

Author(s):

Dinesh Rajasekharan ◽

Sarvesh S. Chauhan ◽

Amit Ranjan Trivedi ◽

Yogesh Singh Chauhan

Keyword(s):

Neural Networks ◽

Spiking Neural Networks ◽

Tunnel Fet ◽

Area Efficient

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Area Efficient FFT/IFFT Processor Design for MIMO OFDM System in Wireless Communication

2015 7th International Conference on Emerging Trends in Engineering & Technology (ICETET) ◽

10.1109/icetet.2015.25 ◽

2015 ◽

Cited By ~ 1

Author(s):

Laxman P. Thakare ◽

A. Y. Deshmukh

Keyword(s):

Wireless Communication ◽

Processor Design ◽

Ofdm System ◽

Mimo Ofdm ◽

Area Efficient

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Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

2006 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2006.311352 ◽

2006 ◽

Cited By ~ 7

Author(s):

Arfan Ghani ◽

T. McGinnity ◽

Liam Maguire ◽

Jim Harkin

Keyword(s):

Neural Networks ◽

Large Scale ◽

Reconfigurable Hardware ◽

Spiking Neural Networks ◽

Area Efficient

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Digital CMOS VLSI processor design for the implementation of neural networks using linear wavefront architecture

Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan) ◽

10.1109/ijcnn.1993.717044 ◽

2005 ◽

Cited By ~ 2

Author(s):

M. Conti ◽

S. Orcioni ◽

F. Piazza ◽

C. Turchetti

Keyword(s):

Neural Networks ◽

Processor Design ◽

Digital Cmos ◽

Cmos Vlsi

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A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

IEEE Transactions on Neural Networks and Learning Systems ◽

10.1109/tnnls.2021.3095068 ◽

2021 ◽

pp. 1-15

Author(s):

Yusuke Sakemi ◽

Kai Morino ◽

Takashi Morie ◽

Kazuyuki Aihara

Keyword(s):

Neural Networks ◽

Supervised Learning ◽

Energy Efficient ◽

Learning Algorithm ◽

Temporal Coding ◽

Spiking Neural Networks ◽

Processor Design

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A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array

IEEE Transactions on Biomedical Circuits and Systems ◽

10.1109/tbcas.2019.2945559 ◽

2019 ◽

Vol 13 (6) ◽

pp. 1678-1689 ◽

Cited By ~ 1

Author(s):

Injune Yeo ◽

Myonglae Chu ◽

Byung-Geun Lee

Keyword(s):

Neural Networks ◽

Crossbar Array ◽

Stochastic Neuron ◽

Area Efficient

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A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks

2012 IEEE 42nd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2012.31 ◽

2012 ◽

Cited By ~ 2

Author(s):

F. Saffar ◽

M. Mirhassani ◽

M. Ahmadi

Keyword(s):

Neural Networks ◽

Fault Tolerant ◽

Current Mode ◽

Area Efficient

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A Multilayer Neural Networks Supervised Learning Algorithm Based Energy-Efficient VLSI Processor Design

Journal of Physics Conference Series ◽

10.1088/1742-6596/1964/6/062042 ◽

2021 ◽

Vol 1964 (6) ◽

pp. 062042

Author(s):

R. Mohanapriya ◽

D. Vijendra Babu ◽

S. SathishKumar ◽

C. Sarala ◽

E. Anjali ◽

...

Keyword(s):

Neural Networks ◽

Supervised Learning ◽

Energy Efficient ◽

Learning Algorithm ◽

Processor Design ◽

Multilayer Neural Networks

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Power and area efficient stochastic artificial neural networks using spin–orbit torque-based true random number generator

Applied Physics Letters ◽

10.1063/5.0035857 ◽

2021 ◽

Vol 118 (5) ◽

pp. 052401

Author(s):

Min Song ◽

Wei Duan ◽

Shuai Zhang ◽

Zhenjiang Chen ◽

Long You

Keyword(s):

Neural Networks ◽

Artificial Neural Networks ◽

Random Number ◽

Random Number Generator ◽

Spin Orbit ◽

Number Generator ◽

True Random Number Generator ◽

Artificial Neural ◽

Area Efficient

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Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/asp-dac47756.2020.9045156 ◽

2020 ◽

Cited By ~ 2

Author(s):

Jiaqi Gu ◽

Zheng Zhao ◽

Chenghao Feng ◽

Mingjie Liu ◽

Ray T. Chen ◽

...

Keyword(s):

Neural Networks ◽

Optical Neural Networks ◽

Area Efficient

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