High-level data path synthesis for built-in self-test designs

2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233) ◽

10.1109/pacrim.2001.953577 ◽

2002 ◽

Author(s):

Laurence Tainruo Yang ◽

J. Muzio

Keyword(s):

Data Path ◽

Self Test ◽

Built In Self Test ◽

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A Verifiable High Level Data Path Synthesis Framework

2012 15th Euromicro Conference on Digital System Design ◽

10.1109/dsd.2012.16 ◽

2012 ◽

Author(s):

Gorker Alp Malazgirt ◽

Ender Culha ◽

Alper Sen ◽

Faik Baskaya ◽

Arda Yurdakul

Keyword(s):

Data Path ◽

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Testability analysis in high level data path synthesis

Journal of Electronic Testing ◽

10.1007/bf00971939 ◽

1993 ◽

Vol 4 (1) ◽

pp. 43-56 ◽

Author(s):

Johannes Steensma ◽

Werner Geurts ◽

Francky Catthoor ◽

Hugo De Man

Keyword(s):

Data Path ◽

Testability Analysis ◽

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SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2011.2106851 ◽

2011 ◽

Vol 30 (6) ◽

pp. 829-840 ◽

Author(s):

Shahin Golshan ◽

Hessam Kooti ◽

Elaheh Bozorgzadeh

Keyword(s):

Data Path ◽

Layout Generation ◽

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A high-level data path allocation algorithm based on BIST testability metrics

The 14th International Conference on Microelectronics, ◽

10.1109/icm-02.2002.1161537 ◽

2004 ◽

Author(s):

L. Tianruo Yang ◽

J. Muzio

Keyword(s):

Data Path ◽

Allocation Algorithm ◽

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High-Level Optimization of Built-In Self Test for Analog to Digital Converters

MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference ◽

10.1109/melcon.2006.1653046 ◽

2006 ◽

Author(s):

D. De Venuto ◽

L. Reyneri

Keyword(s):

Analog To Digital Converters ◽

Analog To Digital ◽

Self Test ◽

Built In Self Test ◽

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An improved high-level built-in self-test synthesis algorithm

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) ◽

10.1109/icecs.2001.957802 ◽

2001 ◽

Keyword(s):

Synthesis Algorithm ◽

Test Synthesis ◽

Self Test ◽

Built In Self Test ◽

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BUILT-IN SELF-TEST FOR HIGH-SPEED DATA-PATH CIRCUITRY

1991, Proceedings. International Test Conference ◽

10.1109/test.1991.519493 ◽

2005 ◽

Author(s):

C.E. Stroud

Keyword(s):

Data Path ◽

High Speed Data ◽

Self Test ◽

Built In Self Test

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High-Level verifiable data-path Synthesis for DSP systems

2012 20th Signal Processing and Communications Applications Conference (SIU) ◽

10.1109/siu.2012.6204710 ◽

2012 ◽

Author(s):

Ender Culha ◽

Gorker Alp Malazgirt ◽

I. Faik Baskaya ◽

Alper Sen ◽

Arda Yurdakul

Keyword(s):

Data Path ◽

Dsp Systems ◽

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Automatic built-in self-test insertion for high level circuit descriptions

Proceedings of Eighth International Application Specific Integrated Circuits Conference ◽

10.1109/asic.1995.580719 ◽

2002 ◽

Author(s):

H. Vilas ◽

C. Gloster

Keyword(s):

Self Test ◽

Built In Self Test ◽

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The High-Level Data-Path Mapping Script

Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications ◽

10.1007/978-1-4419-8720-4_5 ◽

1997 ◽

pp. 63-85

Author(s):

Werner Geurts ◽

Francky Catthoor ◽

Serge Vernalde ◽

Hugo de Man

Keyword(s):

Data Path ◽

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