Operational fault-tolerant microcomputer for very high reliability

1983 ◽  
Vol 130 (3) ◽  
pp. 90 ◽  
Author(s):  
Mashkuri Yaacob ◽  
M.G. Hartley ◽  
P.G. Depledge
1965 ◽  
Vol 180 (1) ◽  
pp. 246-259
Author(s):  
R. Ruggles

The author discusses some of the problems of failure-survival automatic flight control systems and suggests some basic ground rules as design criteria. The advantages and disadvantages of some of the main types of system are discussed: duplex, triplex, triple component, duplicate-monitored and quadruplex systems being covered. In particular, a quadruplex actuator is described which has been designed and developed mainly for automatic flight control system applications where a very high degrees of failure-survival capability is required. A detailed failure analysis of the various systems is carried out and the importance of the electrical and hydraulic supply system configurations and failure rates is brought out.


Author(s):  
S. C. Knowles

The development of the letter code desk is described, particular reference being made to the necessity for the characteristics to be suited to the operating personnel. An explanation is given of the design features introduced as a result of this unit being required in relatively large numbers for this class of work. The development of the special printing unit for code application is described, with particular emphasis on the very high reliability required. An indication is given of probable future trends.


Role of Configurable Distributed Checkout and Launch System (CDCLS) is pivotal in carrying out quick health checks and launching of Aerospace Flight Vehicles. Configurable Distributed Architecture provides flexibility for connecting nodes and scaling Distributed System. Different configurations can be derived from the Master Configuration. Since, Ultra high reliability and infallible performance of the CDCLS is of paramount importance, Safety criticality and Mission criticality analysis needs to be carried out for determination of mission critical parameters. These critical parameters need to be addressed by required fault tolerant architecture, which can be implemented in Hardware and Software for achieving system reliability objective (Say, 0.99).


2019 ◽  
Author(s):  
Kimmo Sorjonen ◽  
Daniel Falkstedt ◽  
Bo Melin ◽  
Michael Ingre

Some studies have analyzed the effect of a predictor measured at a later time point (X1), or of the X1-X0 difference, while adjusting for the predictor measured at baseline (X0), on some outcome Y of interest. The present simulation study shows that, if used to analyze the effect of change in X on Y, there is a high risk for this analysis to produce type 1-errors, especially with a strong correlation between true X and Y, when X0 and X1 are not measured with very high reliability, and with a large sample size. These problems are not encountered if analyzing the unadjusted effect of the X1-X0 difference on Y instead, and as this effect exhibits power on par with the adjusted effect it seems as the preferable method when using change between two measurement points as a predictor.


2014 ◽  
Vol 217-218 ◽  
pp. 471-480
Author(s):  
Ivano Gattelli ◽  
Gian Luigi Chiarmetta ◽  
Marcello Boschini ◽  
Renzo Moschini ◽  
Mario Rosso ◽  
...  

This paper concerns with the optimisation of the innovative rheocasting process to produce a new generation of brake callipers, characterised by very high reliability and strength. The attained very promising properties favoured their use on a very high performance car and the presented technique can be further extended for other important challenging applications. The prototype components are produced using T6 heat treated A357 alloy. Results on the samples machined directly from the produced callipers are in detail described and analysed. Pieces exhibiting some small defects, individuated by non-destructive tests, as well as defectless pieces have been underlined to severe industrial tests, e.g. high pressure tight, as well as severe bench tests, and it has been observed that the proposed technological process assure the fulfilment of the requirements contained in standards.


Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.


Sign in / Sign up

Export Citation Format

Share Document