Performance Analysis of a Double-Gate Junctionless Transistor with Varied Doping and Gate Underlap using Device Simulator

Mapping Intimacies ◽

10.1109/sennano51750.2021.9642547 ◽

2021 ◽

Author(s):

Nurul Nasirah Afiqah Nasir ◽

Noraini Othman ◽

Syarifah Norfaezah Sabki ◽

Alhan Farhanah Abd Rahim

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Junctionless Transistor ◽

Gate Underlap

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Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor

Silicon ◽

10.1007/s12633-021-01335-6 ◽

2021 ◽

Author(s):

Pawandeep Kaur ◽

Avtar Singh Buttar ◽

Balwinder Raj

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Junctionless Transistor ◽

And Performance

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Inverter performance analysis of 3D double gate junctionless transistor

2017 2nd International Conference on Communication and Electronics Systems (ICCES) ◽

10.1109/cesys.2017.8321194 ◽

2017 ◽

Author(s):

Achinta Baidya ◽

T. R. Lenka ◽

S. Baishya

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Junctionless Transistor

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Performance analysis of N-type double gate junctionless transistor

2016 International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES) ◽

10.1109/iceteeses.2016.7581402 ◽

2016 ◽

Author(s):

Shweta Yadav ◽

Vimal Kumar Mishra ◽

R. K. Chauhan

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Junctionless Transistor

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Implementation of double-gate junctionless transistor and its circuit performance analysis

2016 IEEE Students’ Technology Symposium (TechSym) ◽

10.1109/techsym.2016.7872696 ◽

2016 ◽

Author(s):

Rhushikesh K. Joshi ◽

T. V. Arjun ◽

S. Ahish ◽

Dheeraj Sharma ◽

M. H. Vasantha ◽

...

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Circuit Performance ◽

Junctionless Transistor

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Performance analysis and improvement of nanoscale double gate Junctionless transistor based inverter using high-K gate dielectrics

TENCON 2015 - 2015 IEEE Region 10 Conference ◽

10.1109/tencon.2015.7373040 ◽

2015 ◽

Cited By ~ 3

Author(s):

Achinta Baidya ◽

T. R. Lenka ◽

S. Baishya

Keyword(s):

Performance Analysis ◽

Gate Dielectrics ◽

Double Gate ◽

High K ◽

Junctionless Transistor

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Analytical model of gate underlap Double Gate Junctionless MOSFET as a bio-sensor

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2016.7570649 ◽

2016 ◽

Author(s):

Ajay ◽

Rakhi Narang ◽

Manoj Saxena ◽

Mridula Gupta

Keyword(s):

Analytical Model ◽

Double Gate ◽

Gate Underlap

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Effect of Channel Doping Variation on Electrostatic Characteristics of 3D Double Gate Junctionless Transistor

10.1007/978-981-16-2109-3_45 ◽

2021 ◽

pp. 489-497

Author(s):

Achinta Baidya ◽

Rajesh Saha ◽

Jayendra Kumar ◽

Sadhan Gope ◽

Chaitali Koley

Keyword(s):

Double Gate ◽

Junctionless Transistor

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Effect of Au-Al Dual-Metal Gate on 3D Double-Gate Junctionless Transistor Performance

10.1007/978-981-16-2109-3_39 ◽

2021 ◽

pp. 421-429

Author(s):

Achinta Baidya ◽

Rajesh Saha ◽

Amarnath Gaini ◽

Chaitali Koley ◽

Somen Debnath ◽

...

Keyword(s):

Double Gate ◽

Metal Gate ◽

Junctionless Transistor ◽

Dual Metal

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Transport characteristics of double gate n-channel junctionless transistor

2016 9th International Conference on Electrical and Computer Engineering (ICECE) ◽

10.1109/icece.2016.7853938 ◽

2016 ◽

Author(s):

Tanmoy Kumar Paul ◽

Quazi D. M. Khosru

Keyword(s):

Double Gate ◽

Junctionless Transistor

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Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

Microelectronics Reliability ◽

10.1016/j.microrel.2011.02.004 ◽

2011 ◽

Vol 51 (6) ◽

pp. 1105-1112 ◽

Cited By ~ 6

Author(s):

Swagata Bhattacherjee ◽

Abhijit Biswas

Keyword(s):

Performance Analysis ◽

Carrier Concentration ◽

Gate Dielectrics ◽

Double Gate ◽

High K

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