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Implementation of double-gate junctionless transistor and its circuit performance analysis
2016 IEEE Students’ Technology Symposium (TechSym)
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10.1109/techsym.2016.7872696
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2016
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Author(s):
Rhushikesh K. Joshi
◽
T. V. Arjun
◽
S. Ahish
◽
Dheeraj Sharma
◽
M. H. Vasantha
◽
...
Keyword(s):
Performance Analysis
◽
Double Gate
◽
Circuit Performance
◽
Junctionless Transistor
Download Full-text
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Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor
Silicon
◽
10.1007/s12633-021-01335-6
◽
2021
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Author(s):
Pawandeep Kaur
◽
Avtar Singh Buttar
◽
Balwinder Raj
Keyword(s):
Performance Analysis
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Double Gate
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Junctionless Transistor
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And Performance
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Performance Analysis of a Double-Gate Junctionless Transistor with Varied Doping and Gate Underlap using Device Simulator
10.1109/sennano51750.2021.9642547
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2021
◽
Author(s):
Nurul Nasirah Afiqah Nasir
◽
Noraini Othman
◽
Syarifah Norfaezah Sabki
◽
Alhan Farhanah Abd Rahim
Keyword(s):
Performance Analysis
◽
Double Gate
◽
Junctionless Transistor
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Gate Underlap
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Inverter performance analysis of 3D double gate junctionless transistor
2017 2nd International Conference on Communication and Electronics Systems (ICCES)
◽
10.1109/cesys.2017.8321194
◽
2017
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Author(s):
Achinta Baidya
◽
T. R. Lenka
◽
S. Baishya
Keyword(s):
Performance Analysis
◽
Double Gate
◽
Junctionless Transistor
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Performance analysis of N-type double gate junctionless transistor
2016 International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES)
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10.1109/iceteeses.2016.7581402
◽
2016
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Author(s):
Shweta Yadav
◽
Vimal Kumar Mishra
◽
R. K. Chauhan
Keyword(s):
Performance Analysis
◽
Double Gate
◽
Junctionless Transistor
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Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm
The Journal of Engineering
◽
10.1049/joe.2013.0269
◽
2014
◽
Vol 2014
(3)
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pp. 105-110
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Cited By ~ 8
Author(s):
Chitrakant Sahu
◽
Jawar Singh
Keyword(s):
Performance Analysis
◽
Double Gate
◽
Circuit Performance
◽
Junctionless Transistors
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Performance analysis and improvement of nanoscale double gate Junctionless transistor based inverter using high-K gate dielectrics
TENCON 2015 - 2015 IEEE Region 10 Conference
◽
10.1109/tencon.2015.7373040
◽
2015
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Cited By ~ 3
Author(s):
Achinta Baidya
◽
T. R. Lenka
◽
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Keyword(s):
Performance Analysis
◽
Gate Dielectrics
◽
Double Gate
◽
High K
◽
Junctionless Transistor
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Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis
The Fifth International Conference on VLSI Design
◽
10.1109/icvd.1992.658079
◽
2005
◽
Cited By ~ 1
Author(s):
A. Dharchoudhury
◽
S.M. Kang
Keyword(s):
Performance Analysis
◽
Worst Case
◽
Circuit Performance
◽
Model Parameter
◽
Device Model
◽
Parameter Values
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Spacer Effects on the Circuit Performance of DG Junctionless Transistor
2018 Conference on Emerging Devices and Smart Systems (ICEDSS)
◽
10.1109/icedss.2018.8544317
◽
2018
◽
Author(s):
Adhithan Pon
◽
M. Madheswaran
◽
A. Santhia Carmel
◽
A. Bhattacharyya
◽
R. Ramesh
Keyword(s):
Circuit Performance
◽
Junctionless Transistor
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Effect of Channel Doping Variation on Electrostatic Characteristics of 3D Double Gate Junctionless Transistor
10.1007/978-981-16-2109-3_45
◽
2021
◽
pp. 489-497
Author(s):
Achinta Baidya
◽
Rajesh Saha
◽
Jayendra Kumar
◽
Sadhan Gope
◽
Chaitali Koley
Keyword(s):
Double Gate
◽
Junctionless Transistor
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Effect of Au-Al Dual-Metal Gate on 3D Double-Gate Junctionless Transistor Performance
10.1007/978-981-16-2109-3_39
◽
2021
◽
pp. 421-429
Author(s):
Achinta Baidya
◽
Rajesh Saha
◽
Amarnath Gaini
◽
Chaitali Koley
◽
Somen Debnath
◽
...
Keyword(s):
Double Gate
◽
Metal Gate
◽
Junctionless Transistor
◽
Dual Metal
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