Equations for the Electron Density of the Two-Dimensional Electron Gas in Realistic AlGaN/GaN Heterostructures

This paper presents equations for the electron density of the two-dimensional electron gas (2DEG) in AlGaN/GaN heterostructures in three realistic scenarios: (1) AlGaN/GaN heterostructure with surface exposed to ambient with mobile ions, (2) metal gate deposited on the AlGaN surface, and (3) a thick dielectric passivation layer on the AlGaN surface. To derive the equations, we analyzed these scenarios by applying Gauss’s law. In contrast to the idealistic models, our analysis shows that the 2DEG charge density is proportional to the difference between spontaneous polarization of AlGaN and GaN, whereas surprisingly, it is independent of the piezoelectric polarization.

Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in-situ deposited Al2O3/Y2O3 as a gate dielectric

We have demonstrated a record low 85 mV/dec subthreshold slope (SS) at 300 K among the planar inversion-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). Our MOSFETs using in-situ deposited Al2O3/Y2O3 as a gate dielectric were fabricated with a self-aligned inversion-channel metal-gate-first process. The temperature-dependent transfer characteristics showed a linear reduction of SS versus temperature, with attainment of an SS of 22 mV/dec at 77 K; the value is comparable to that of the state-of-the-art InGaAs FinFET. The slope factor of SS with temperature (m) is 1.33, which is lower than those reported in the planar InGaAs MOSFETs.

Studies on electrical characteristics of HKMG MOS capacitor by high pressure annealing

High pressure annealing technique at 6 atm over a wide range of temperature (200-450˚C) was introduced as post metal annealing on high-k/metal gate metal-oxide-semiconductor capacitor. To verify the ability of HPA in improving interface trap density, leakage issue the other MOS capacitor with same structure was annealed by MWA for comparison. The electrical performance of the capacitors under different etching mechanism was analyzed and the difference in characteristics such as flat-band voltage shift, oxide trapped charge, interface state density and leakage current were compared. The results show that high pressure annealing process is more effective to minimize the oxide trapped charged at low temperature than by high power MWA at 3000W, and the reduction in leakage current density after high pressure anneal at low temperature corresponds to the reduction in charge traps. High pressure annealing demonstrates great potential as the post-metallization annealing process for the high-k/metal gate structure .