A novel digital loop filter architecture for bang-bang ADPLL

2012 IEEE International SOC Conference ◽

10.1109/socc.2012.6398378 ◽

2012 ◽

Author(s):

Moataz Abdelfattah ◽

Maged Ghoneima ◽

Yehea I. Ismail ◽

Amr Lotfy ◽

Mohamed Abdelsalam ◽

...

Keyword(s):

Loop Filter ◽

Filter Architecture ◽

Digital Loop Filter

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Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2007.907171 ◽

2007 ◽

Vol 42 (11) ◽

pp. 2503-2514 ◽

Author(s):

Adrian Maxim

Keyword(s):

Frequency Synthesizer ◽

Loop Filter ◽

Feed Forward ◽

Feed Forward Loop ◽

Filter Architecture ◽

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A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2009.2039530 ◽

2010 ◽

Vol 45 (3) ◽

pp. 578-586 ◽

Author(s):

Song-Yu Yang ◽

Wei-Zen Chen ◽

Tai-You Lu

Keyword(s):

Frequency Synthesizer ◽

Cmos Technology ◽

Loop Filter ◽

Digital Frequency ◽

Digital Loop Filter

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Frequency synthesizer using a hybrid analog/digital loop filter: A low complexity approach

AEU - International Journal of Electronics and Communications ◽

10.1016/j.aeue.2011.02.002 ◽

2011 ◽

Vol 65 (10) ◽

pp. 888-891 ◽

Author(s):

Vlademir J.S. Oliveira ◽

Nobuo Oki

Keyword(s):

Frequency Synthesizer ◽

Low Complexity ◽

Loop Filter ◽

Digital Loop Filter

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A novel digital loop filter with frequency error prediction for fast-locking bang-bang ADPLL

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2017.8333239 ◽

2017 ◽

Author(s):

Linqi Shi ◽

Weixin Gai ◽

Liangxiao Tang ◽

Xiao Xiang

Keyword(s):

Error Prediction ◽

Frequency Error ◽

Loop Filter ◽

Digital Loop Filter

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A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) ◽

10.1109/esscirc.2019.8902785 ◽

2019 ◽

Author(s):

Mario Auer ◽

Timucin Karaca

Keyword(s):

Feedback Loop ◽

Loop Filter ◽

Mixed Signal ◽

Class D Amplifier ◽

Class D ◽

Digital Loop Filter

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A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers ◽

10.1109/isscc.2006.1696175 ◽

2006 ◽

Author(s):

M.H. Perrott ◽

Yunteng Huang ◽

R.T. Baird ◽

B.W. Garlepp ◽

Ligang Zhang ◽

...

Keyword(s):

Loop Filter ◽

Digital Loop Filter

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The design and simulations of phase and timing tracking circuits with pre-assured 2nd order digital loop filter

2011 International Conference on Electrical and Control Engineering ◽

10.1109/iceceng.2011.6057919 ◽

2011 ◽

Author(s):

Chien-Hsing Liao ◽

Fu-Nian Ku ◽

Fu-Hao Yeh ◽

Jia-Chin Lin ◽

Mu-King Tsay

Keyword(s):

Loop Filter ◽

Digital Loop Filter

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Scalable high performance loop filter architecture for video codecs

2013 IEEE Second International Conference on Image Information Processing (ICIIP-2013) ◽

10.1109/iciip.2013.6707621 ◽

2013 ◽

Author(s):

Niraj Nandan ◽

Mihir Mody

Keyword(s):

High Performance ◽

Loop Filter ◽

Video Codecs ◽

Filter Architecture

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A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO

2016 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2016.7538882 ◽

2016 ◽

Author(s):

Amr Lotfy ◽

Maged Ghoneima ◽

Mohamed Abdel-Moneum

Keyword(s):

Loop Filter ◽

Digital Loop Filter

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A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients

2011 International Conference on Energy Aware Computing ◽

10.1109/iceac.2011.6136676 ◽

2011 ◽

Author(s):

Sally Safwat ◽

Maged Ghoneima ◽

Yehea Ismail

Keyword(s):

Low Power ◽

Design Methodology ◽

Loop Filter ◽

Digital Loop Filter

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