A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

2010 ◽  
Vol 45 (3) ◽  
pp. 578-586 ◽  
Author(s):  
Song-Yu Yang ◽  
Wei-Zen Chen ◽  
Tai-You Lu
Keyword(s):  
Frequency Synthesizer ◽  
Cmos Technology ◽  
Loop Filter ◽  
Digital Frequency ◽  
Digital Loop Filter

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

Design of a High-Frequency Very Low-Power Direct Digital Frequency Synthesizer

2016 ◽  
Vol 25 (08) ◽  
pp. 1650085 ◽  
Author(s):  
Mojtaba Hasannezhad ◽  
Abumoslem Jannesari ◽  
Mojtaba Lotfizad
Keyword(s):  
Low Power ◽  
Frequency Synthesizer ◽  
Dynamic Range ◽  
Design Method ◽  
Cmos Technology ◽  
Frequency Resolution ◽  
Digital Frequency ◽  
Spurious Free Dynamic Range ◽  
Frequency Independent ◽  
Direct Digital Frequency Synthesizer

This paper presented a low-power Direct Digital Frequency Synthesizer (DDFS) using non-uniform sine-weighted digital-to-analog convertor (DAC). To avoid the need for a sharp filter to generate signals near and beyond the Nyquist frequency, parallel DACs, which cause to speed relaxation in a single DAC as well, and return-to-zero (RZ) technique were used. To reduce the area and power in parallel DACs, non-uniform sine-weighted DAC design method was proposed. This technique causes to reduce power consumption in DACs up to 48.47%, and nearly the same amount of reduction in the area. Meanwhile, by modifying weights of DAC cells, Gilbert cell, the latter block in DDFS structure, was omitted. Although these proposed methods are quite frequency independent, simulations with MATLAB and Cadence in 0.18[Formula: see text][Formula: see text]m CMOS technology were used to demonstrate those. Then, the designed DDFS with 5-bit frequency resolution could generate different output sine signals with acceptable spurious free dynamic range (SFDR).

Low Power, Wide Range Synthesizer for 534MHz–18.56GHz Band with FoM of −192.45dBc/Hz

2021 ◽  
pp. 2250032
Author(s):  
Gaurav Kumar Sharma ◽  
Arun Kishor Johar ◽  
D. Boolchandani
Keyword(s):  
Figure Of Merit ◽  
Satellite Communication ◽  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Wide Spectrum ◽  
Charge Pump ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Loop Filter ◽  
Wide Range

A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534[Formula: see text]MHz to 18.56[Formula: see text]GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0[Formula: see text]V) of select input generates frequencies from 534[Formula: see text]MHz to 5.08[Formula: see text]GHz whereas logic high value (1.1[Formula: see text]V) of select input enables the frequency generation in the range of 5.08[Formula: see text]GHz to 18.56[Formula: see text]GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1[Formula: see text]V. Power consumption of the proposed circuits is 2.88[Formula: see text]mW while generating frequency of 7.84[Formula: see text]GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of [Formula: see text][Formula: see text]dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.

scholarly journals Design of All Digital Phase Locked Loop for Wireless Applications

2018 ◽  
Vol 7 (3.12) ◽  
pp. 836
Author(s):  
Swetha R ◽  
J Manjula ◽  
A Ruhan bevi
Keyword(s):  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detector ◽  
Ring Oscillator ◽  
Frequency Range ◽  
Loop Filter ◽  
Wireless Applications ◽  
Digital Phase ◽  
Operating Frequency Range

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW. 

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