A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems
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2009 ◽
Vol E92-C
(7)
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pp. 922-928
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2006 ◽
Vol 21
(5)
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pp. 464-472
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2009 ◽
Vol 2009
(8)
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pp. 67-71
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