Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem

2021 ◽  
pp. 1-1
Author(s):  
Saravanan Sethuraman ◽  
Venkata Kalyan Tavva ◽  
M. B. Srinivas
Keyword(s):  
Memory Subsystem

How does processor MHz relate to end-user performance? II. Memory subsystem and instruction set

IEEE Micro ◽  
1993 ◽  
Vol 13 (5) ◽  
pp. 79-89 ◽  
Author(s):  
S.W. White ◽  
P.D. Hester ◽  
J.W. Kemp ◽  
G.J. McWilliams
Keyword(s):  
Instruction Set ◽  
User Performance ◽  
End User ◽  
Memory Subsystem

scholarly journals Implementation of Memory Subsystem of Cycle-Accurate Application-Level Simulator of the Elbrus Microprocessors

2020 ◽  
Vol 32 (2) ◽  
pp. 61-80
Author(s):  
Pavel Alexeevitch Poroshin ◽  
Dmitry Valerievich Znamenskiy ◽  
Alexey Nikolaevitch Meshkov
Keyword(s):  
Memory Subsystem

Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels

2012 ◽  
pp. 278-296
Author(s):  
Dake Liu ◽  
Joar Sohl ◽  
Jian Wang
Keyword(s):  
Signal Processing ◽  
Parallel Programming ◽  
High Performance ◽  
Data Access ◽  
Time Signal ◽  
Hardware System ◽  
Memory Subsystem ◽  
Computing Performance ◽  
Processing Platform ◽  
Parallel Signal Processing

A novel master-multi-SIMD architecture and its kernel (template) based parallel programming flow is introduced as a parallel signal processing platform. The name of the platform is ePUMA (embedded Parallel DSP processor architecture with Unique Memory Access). The essential technology is to separate data accessing kernels from arithmetic computing kernels so that the run-time cost of data access can be minimized by running it in parallel with algorithm computing. The SIMD memory subsystem architecture based on the proposed flow dramatically improves the total computing performance. The hardware system and programming flow introduced in this article will primarily aim at low-power high-performance embedded parallel computing with low silicon cost for communications and similar real-time signal processing.

scholarly journals WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

ETRI Journal ◽  
2017 ◽  
Vol 39 (3) ◽  
pp. 428-436 ◽  
Author(s):  
Wooyoung Jang
Keyword(s):  
Memory Subsystem

New access modes of parallel memory subsystem for sub-pixel motion estimation

2014 ◽  
Vol 15 (2) ◽  
pp. 279-296 ◽  
Author(s):  
Radomir Jakovljević ◽  
Aleksandar Berić ◽  
Edwin van Dalen ◽  
Dragan Milićev
Keyword(s):  
Motion Estimation ◽  
Parallel Memory ◽  
Memory Subsystem
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