A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2017.2689029 ◽

2018 ◽

Vol 65 (3) ◽

pp. 281-285 ◽

Author(s):

Dong-Jin Chang ◽

Min-Jae Seo ◽

Hyeok-Ki Hong ◽

Seung-Tak Ryu

Keyword(s):

Low Power ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset

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Static Phase Offset in a Multiplying Phase Detector

IEEE Microwave and Wireless Components Letters ◽

10.1109/lmwc.2009.2024844 ◽

2009 ◽

Vol 19 (8) ◽

pp. 518-520 ◽

Author(s):

J. Carr ◽

B. Frank

Keyword(s):

Phase Detector ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset

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Static Phase Offset Reduction Technique for Delay Locked Loops

2019 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2019.8702613 ◽

2019 ◽

Author(s):

Chithra ◽

Nagendra Krishnapura

Keyword(s):

Reduction Technique ◽

Phase Offset ◽

Delay Locked Loops ◽

Static Phase ◽

Static Phase Offset

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1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2013.0023 ◽

2013 ◽

Vol 7 (3) ◽

pp. 159-168 ◽

Author(s):

Sangjin Byun ◽

Chung Hwan Son ◽

Jongil Hwang ◽

Byung‐Hun Min ◽

Mun‐Yang Park ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset

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A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

Circuits and Systems ◽

10.4236/cs.2015.61002 ◽

2015 ◽

Vol 06 (01) ◽

pp. 13-19 ◽

Author(s):

Xinjie Wang ◽

Tadeusz Kwasniewski

Keyword(s):

Reduction Technique ◽

Delay Locked Loop ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset

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A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset

2009 27th IEEE VLSI Test Symposium ◽

10.1109/vts.2009.36 ◽

2009 ◽

Author(s):

Keith A. Jenkins ◽

Lionel Li

Keyword(s):

Phase Offset ◽

Static Phase ◽

Static Phase Offset

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A 0.2–1.45-GHz Subsampling Fractional- $N$ Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2016.2638432 ◽

2017 ◽

Vol 52 (3) ◽

pp. 799-811 ◽

Author(s):

Somnath Kundu ◽

Bongjin Kim ◽

Chris H. Kim

Keyword(s):

Phase Offset ◽

Static Phase ◽

Zero Offset ◽

Static Phase Offset

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A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter

Microelectronics Journal ◽

10.1016/j.mejo.2020.104926 ◽

2020 ◽

Vol 106 ◽

pp. 104926

Author(s):

Jin Wu ◽

Shuang Chen ◽

Kang Hu ◽

Lixia Zheng ◽

Weifeng Sun

Keyword(s):

Digital Converter ◽

Time To Digital Converter ◽

Delay Locked Loop ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset

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Edge-combining multi-phase DLL frequency multiplier with reduced static phase offset and linearized delay transfer curve

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-015-0495-1 ◽

2015 ◽

Vol 82 (3) ◽

pp. 705-718 ◽

Author(s):

Mostafa Hassani ◽

Saeed Saeedi

Keyword(s):

Frequency Multiplier ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset ◽

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Chopping of phase frequency detector to remove static phase offset in PLLs and MDLLs

Irish Signals and Systems Conference 2004 ◽

10.1049/cp:20040527 ◽

2004 ◽

Author(s):

I.M. Kennedy

Keyword(s):

Phase Frequency Detector ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset ◽

Frequency Detector

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A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection

2013 IEEE 31st VLSI Test Symposium (VTS) ◽

10.1109/vts.2013.6548912 ◽

2013 ◽

Author(s):

Sen-Wen Hsiao ◽

Nicholas Tzou ◽

A. Chatterjee

Keyword(s):

Phase Offset ◽

Static Phase ◽

Static Phase Offset ◽

Cycle Detection

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