A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification

2005 ◽  
Vol 28 (4) ◽  
pp. 344-354 ◽  
Author(s):  
Chunho Kim ◽  
D.F. Baldwin
Keyword(s):  
Experimental Verification ◽  
Assembly Process ◽  
Yield Model ◽  
Solder Interconnect ◽  
Theoretical Yield ◽  
Area Array

Analysis and Modeling of Lead Coplanarity Distributions

1996 ◽  
Vol 118 (4) ◽  
pp. 201-205 ◽  
Author(s):  
E. K. Buratynski
Keyword(s):  
Probability Distribution ◽  
Assembly Process ◽  
Yield Model ◽  
Surface Mount ◽  
Parameter Variations

Lead coplanarity is defined as the height of a packaged device lead above the seating plane on which the device rests. The yield of a mass reflow surface mount soldering assembly process depends on lead coplanarity since, clearly, an excessive coplanarity is likely to produce an “open” between the lead and circuit pad. Furthermore, even if a marginal joint is obtained, excessive coplanarity can lead to reliability problems. Since these issues become more important as lead sizes decrease and pitches are refined, it is important to achieve a better understanding of coplanarity. This report analyzes the nature of 86,016 coplanarity measurements of 0.4 mm pitch, 256 I/O QFP devices. Four components to the coplanarity are identified and the distribution of each is modeled. When the four components are recombined, the result is a probability distribution for coplanarity. This information is required as input to an assembly yield model where parameter variations and tolerances are analyzed to predict surface mount yields.

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