scholarly journals Single-Error Detection and Correction for Duplication and Substitution Channels

2020 ◽  
Vol 66 (11) ◽  
pp. 6908-6919
Author(s):  
Yuanyuan Tang ◽  
Yonatan Yehezkeally ◽  
Moshe Schwartz ◽  
Farzad Farnoud
Author(s):  
AJILESH RK ◽  
ANAND K ◽  
NANDAKUMAR. R ◽  
SREEJEESH.S. G

This paper addresses the design & implementation of configurable Intellectual Property (IP) core for double error detection and single error Correction. The encoding /decoding algorithms considered in this can be implemented with a simple and faster hardware. The block can be used for coding and decoding word having any length and correct single bit error occurred and detect double bit error, during transmission. The user can define the word length and the hamming bits required.


Author(s):  
Gary Gordon ◽  
Elizabeth McMahon

This chapter considers two fundamental questions for detecting and correcting errors made while playing the card game SET®. The game is played with a special deck of eighty-one cards, and the objective is to find three cards that form a set. Over the course of a game, a player may make a mistake by taking three cards that do not form a set—a common occurrence which this chapter examines by first introducing coordinates for the cards and then uses these coordinates to define a Hamming weight for any subset of cards. The chapter then uses the facts about Hamming weight to describe a variant of the game, called the EndGame, which leads to error detection. Afterward, the chapter produces a perfect, single-error-correcting linear code solely from SET® cards. It concludes with additional topics that demonstrate the deep connections between the simple card game and advanced mathematics.


Author(s):  
K. K. GHOUSE ◽  
S ARUNA MASTANI

A novel method develops a built-in self-detection and correction (BISDC) architecture for motion estimation computing arrays(MECAs).Based on the error detection & correction concepts of biresidue codes, any single error in each processing element in an MECA can be effectively detected and corrected online using the proposed BISD and built-in selfcorrection circuits. Performance analysis and evaluation demonstrate that the proposed BISDC architecture performs well in error detection and correction with minor area i.e single error bit detection and correction . An advanced model has been proposed for multi bit detection using efficient adder implementation .a comparision is performed between efficient adder and processing element resultant .


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