DESIGN OF CONFIGURABLE IP CORE FOR ERROR DETECTION AND CORRECTION
2014 ◽
pp. 198-201
Keyword(s):
Ip Core
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This paper addresses the design & implementation of configurable Intellectual Property (IP) core for double error detection and single error Correction. The encoding /decoding algorithms considered in this can be implemented with a simple and faster hardware. The block can be used for coding and decoding word having any length and correct single bit error occurred and detect double bit error, during transmission. The user can define the word length and the hamming bits required.
Keyword(s):
2018 ◽
Vol 2
(2)
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pp. 63
Keyword(s):
2019 ◽
Vol 2019
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pp. 1-15
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Keyword(s):
2010 ◽
Vol 20-23
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pp. 958-962
1977 ◽
Vol 29
(4)
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pp. 727-743
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2020 ◽
Vol 43
(2)
◽
pp. 169-195
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2012 ◽
Vol 12
(4)
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pp. 418-425
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