A LOW POWER NEW DATA COMPRESSION ALGORITHM FOR WIRE/WIRELESS SENSOR NETWORKS USING K-RLE

In this project, we propose and evaluate a new data compression algorithm inspired from Run Length Encoding called K-RLE which means RLE with a K-Precision. This increases the ratio compression compared to RLE. In order to improve the compression results with different statistics of data sources. Here we want to introduce in-network processing technique in order to save energy. In-network processing techniques allow the reduction of the amount of data to be transmitted. The well known in-network processing technique is data compression and/or data aggregation. Data compression is a process that reduces the amount of data in order to reduce data transmitted and/or decreases transfer time because the size of the data is reduced.

AUTONOMOUS RECONFIGURATION OF IP CORE UNITS USING BLRB ALGORITHM

In commercial architectures, the routing consumes most of the chip area, and is responsible for most of the circuit delay. In this paper a new technique of reconfiguring FPGA circuits is proposed. The proposed technique uses BLRB approach for reconfiguring the FPGA. By this approach the routing path is less and the overall delay required to recover from fault is very less. Whenever any fault occurs the spare is selected in such way that whichever spare is nearer is chosen for reconfiguration. By selecting the nearest spare the routing path is decreased. In this method multiple faults are reconfigured at a time and the reconfigured bits are generated.

DECOUPLING LOGIC BASED SRAM DESIGN FOR POWER REDUCTION IN FUTURE MEMORIES

In this paper we are going to modify the column decoupled SRAM for the purpose of more reduced leakages than the existing type of designs as well as the new design which is combined of virtual grounding with column decoupling logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors the simulations were done using microwind & DSCH results

OFFLINE SIGNATURE VERIFICATION BASED ON GLCM

Several papers have recently appeared in the literature which propose pseudo-dynamic features for automatic static handwritten signature verification based on the use of gray level values from signature stroke pixels. Good results have been obtained using rotation invariant uniform local binary patternsLBP plus LBP and statistical measures from gray levelco-occurrence matrices (GLCM) with MCYT and GPDS offline signature corpuses. In these studies the corpuses contain signatures written on a uniform white “nondistorting” background, however the gray level distribution of signature strokes changes when it is written on a complex background, such as a check or an invoice. The aim of this paper is to measure gray level features robustness when it is distorted by a complex background and also to propose more stable features. A set of different checks and invoices with varying background complexity is blended with the MCYT and GPDS signatures. The blending model is based on multiplication. The signature models are trained with genuine signatures on white background and tested with other genuine and forgeries mixed with different backgrounds. Results show that a basic version of local binary patterns (LBP) or local derivative and directional patterns are more robust than rotation invariant uniform LBP or GLCM features to the gray level distortion when using a support vector machine with histogram oriented kernels as a classifier.

A NEW LOW POWER TECHNOLOGY FOR POWER REDUCTION IN SRAM’S USING READ STABILITY WITH REDUCED TRANSISTOR COUNT FOR FUTURE CACHES

In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results.

IMPLEMENTATION OF MULTITRACK SIMULATOR IN FPGA FOR ESM SYSTEM

This project PDW Simulator aims at developing a simulator which can be used to test the processor in the absence of Receiver hardware. This simulates the 128 bit PDW along with the required control signals which will be generated by the receiver card ESM Processor. The 128 bit PD Word is organized as four 32 bit words. Two address bits are used to indicate the word address. A strobe is to be provided to indicate the presence of each word. The simulator is being planned to be developed using Xilinx ISE 10.1 and the simulated results are to be demonstrated on Modelsim simulator or on Xilinx simulator itself.

CRBBE ALGORITHM FOR LOW POWER AND HIGH SPEED MULTIPLIER DESIGN

With the advent of the VLSI technology, designers could design simple chips with the more number of transistors. multipliers have large area, long latency and consume considerable power. Reduction of power consumption makes a device reliable. and The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition, a high-radix-modified booth encoding algorithm is desired. However its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary(NB) to RB conversion. This paper proposes new RB booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent booth encoded digits to directly from an RB partial product to avoid the hard multiple of high-radix booth encoding without incurring any correction vector, and the algorithm achieved high speed compared to existing multiplication algorithms for a gamut of power –of-to word lengths up to 64 b.

MINIATURE IMPROVED CARRY SELECT ADDER WITH ADVANCE FEATURES AND POWER REQUIREMENTS

In most of the data processing processors to perform arithmetic functions Carry Select Adder (CSLA) is used as this is one of the fastest adders. In order to increase the overall efficiency of the processor we can reduce the area and power consumption of the CSLA of processors. Based on this premise we can modify the regular SQRT CSLA architecture as 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

DESIGN OF IMPROVED PERFORMANCE RECTANGULAR MICROSTRIP PATCH ANTENNA USING PEACOCK AND STAR SHAPED DGS

In this paper, two novel defected ground structures (DGS) are proposed to improve the return loss, compactness, gain and radiation efficiency of rectangular microstrip patch antenna. The performance of antenna is characterized by the shape, dimension & the location of DGS at specific position on ground plane. By incorporating a peacock shaped slot of optimum geometries at suitable location on the ground plane, return loss is enhanced from -23.89 dB to -43.79 dB, radiation efficiency is improved from 97.66% to 100% and compactness of 9.83% is obtained over the traditional antenna .Simulation results shows that the patch antenna with star shaped DGS can improve the impedance matching with better return loss of -35.053 dB from -23.89 dB and compactness of 9% is achieved. In the end comparison of both DGS shapes is carried out to choose one best optimize one. The proposed antennas are simulated and analyzed using Ansoft HFSS (version 11.1) software.

A NOVEL FEATURE EXPANSION ALGORITHM FOR NONRIGID CT/MRI BRAIN IMAGE REGISTRATION

Image registration is one of the challenging tasks in medical image analysis. While coming to non rigid image registration there are mainly two issues to consider. They are i) intensity similarity and ii) gray level transformation. The issue with intensity similarity is it is not necessarily equivalent to anatomical similarity when the anatomical correspondences between source and target images are established. Another issue is choosing an appropriate registration algorithm. It should be robust against monotonic gray-level transformation when aligning anatomical structures in the presence of bias fields. Here new feature- intensity based registration method developed for nonrigid brain image registration to overcome the above stated issues named as Anatomical Region Descriptor (ARD). This method is developed on image feature, it encodes geometric properties of anatomical structures and pixel wise interaction details. It is efficient and theoretically monotonic gray level transformation invariant. This method is integrated with intensity based registration algorithm named as residual complexity for Registration purpose. This proposed method is compared with three other non rigid image registration algorithms. Experimental results of the proposed method show that it achieves the highest accuracy rate among the compared methods.