A Simple Method to Estimate the Output Power and Efficiency Load–Pull Contours of Class-B Power Amplifiers

2015 ◽  
Vol 63 (4) ◽  
pp. 1239-1249 ◽  
Author(s):  
Jose C. Pedro ◽  
Luis C. Nunes ◽  
Pedro M. Cabral
2009 ◽  
Vol 1 (4) ◽  
pp. 301-307 ◽  
Author(s):  
Mattias Ferndahl ◽  
Ted Johansson ◽  
Herbert Zirath

The use of 130-nm CMOS for power amplifiers at 20 GHz is explored through a set of power amplifiers as well as transistor level measurements. The power amplifiers explore single versus cascode configuration, smaller versus larger transistor sizes, and the combination of two amplifiers using power splitters/combiners. A maximum output power of 63 mW at 20 GHz was achieved. Transistor-level characterization using load pull measurements on 1-mm gate width transistors yielded 148-mW/mm output power. Transistor modeling and layout for power amplifiers are also discussed. An estimate on the maximum achievable output at 20 GHz from 130-nm CMOS power amplifiers, based on findings in this paper and the literature, is finally presented.


2009 ◽  
Vol 57 (4) ◽  
pp. 881-889 ◽  
Author(s):  
Seok Joo Doo ◽  
P. Roblin ◽  
V. Balasubramanian ◽  
R. Taylor ◽  
K. Dandu ◽  
...  

2005 ◽  
Vol 40 (10) ◽  
pp. 2054-2060 ◽  
Author(s):  
A. Wakejima ◽  
T. Asano ◽  
T. Hirano ◽  
M. Funabashi ◽  
K. Matsunaga

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