Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory

2014 ◽  
Vol 22 (5) ◽  
pp. 1004-1015 ◽  
Author(s):  
Jonghong Kim ◽  
Wonyong Sung
Keyword(s):  
Error Correction ◽  
Flash Memory ◽  
Nand Flash ◽  
Soft Decision ◽  
Nand Flash Memory ◽  
Decision Error ◽  
Ldpc Decoding

Hybrid hard-/soft-decision LDPC decoding strategy for NAND flash memory

2014 ◽  
Vol 59 (28) ◽  
pp. 3554-3561 ◽  
Author(s):  
Wenzhe Zhao ◽  
Guiqiang Dong ◽  
Hongbin Sun ◽  
Tong Zhang ◽  
Nanning Zheng
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Soft Decision ◽  
Nand Flash Memory ◽  
Ldpc Decoding

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory

2019 ◽  
Vol 38 (12) ◽  
pp. 2312-2320 ◽  
Author(s):  
Meng Zhang ◽  
Fei Wu ◽  
Yajuan Du ◽  
Weihua Liu ◽  
Changsheng Xie
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Ldpc Decoding
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