On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory

2011 ◽  
Vol 58 (2) ◽  
pp. 429-439 ◽  
Author(s):  
Guiqiang Dong ◽  
Ningde Xie ◽  
Tong Zhang
Keyword(s):  
Error Correction ◽  
Flash Memory ◽  
Error Correction Codes ◽  
Nand Flash ◽  
Soft Decision ◽  
Nand Flash Memory ◽  
Decision Error

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

scholarly journals Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices

Sensors ◽  
2020 ◽  
Vol 20 (10) ◽  
pp. 2952 ◽  
Author(s):  
Seung-Ho Lim ◽  
Ki-Woong Park
Keyword(s):  
Flash Memory ◽  
Error Recovery ◽  
Recovery Phase ◽  
Error Correction Codes ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Storage ◽  
Storage Devices ◽  
Complementary Method ◽  
Compressed Data

NAND flash memory-based storage devices are vulnerable to errors induced by NAND flash memory cells. Error-correction codes (ECCs) are integrated into the flash memory controller to correct errors in flash memory. However, since ECCs show inherent limits in checking the excessive increase in errors, a complementary method should be considered for the reliability of flash storage devices. In this paper, we propose a scheme based on lossless data compression that enhances the error recovery ability of flash storage devices, which applies to improve recovery capability both of inside and outside the page. Within a page, ECC encoding is realized on compressed data by the adaptive ECC module, which results in a reduced code rate. From the perspective of outside the page, the compressed data are not placed at the beginning of the page, but rather is placed at a specific location within the page, which makes it possible to skip certain pages during the recovery phase. As a result, the proposed scheme improves the uncorrectable bit error rate (UBER) of the legacy system.

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