A 250 MHz-to-1.6 GHz Phase Locked Loop Design in Hybrid FinFET-Memristor Technology

2020 11th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON) ◽

10.1109/uemcon51285.2020.9298155 ◽

2020 ◽

Author(s):

Naheem Olakunle Adesina ◽

Ashok Srivastava

Keyword(s):

Phase Locked Loop ◽

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Fractional-N phase locked loop design and applications

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415633 ◽

2007 ◽

Author(s):

Richard Gu ◽

Sridhar Ramaswamy

Keyword(s):

Phase Locked Loop ◽

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Quantum theory of optical temporal phase and instantaneous frequency. II. Continuous-time limit and state-variable approach to phase-locked loop design

Physical Review A ◽

10.1103/physreva.79.053843 ◽

2009 ◽

Vol 79 (5) ◽

Author(s):

Mankei Tsang ◽

Jeffrey H. Shapiro ◽

Seth Lloyd

Keyword(s):

Quantum Theory ◽

Instantaneous Frequency ◽

Continuous Time ◽

Phase Locked Loop ◽

State Variable ◽

Loop Design ◽

Temporal Phase ◽

Variable Approach

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Comparison and analysis of various PFD architecture for a phase locked loop design

2013 IEEE International Conference on Computational Intelligence and Computing Research ◽

10.1109/iccic.2013.6724238 ◽

2013 ◽

Author(s):

N. K. AnushKannan ◽

H. Mangalam ◽

V. Anoor Dharani ◽

G. Divya ◽

N. Esack ◽

...

Keyword(s):

Phase Locked Loop ◽

Loop Design ◽

Comparison And Analysis

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Phase Locked Loop Design

Commercial Wireless Circuits and Components Handbook ◽

10.1201/9781315220321-8 ◽

2018 ◽

pp. 8-1-8-26

Author(s):

Robert Newgard

Keyword(s):

Phase Locked Loop ◽

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High performance CMOS amplifier and phase-locked loop design

10.31274/rtd-180813-13134 ◽

2002 ◽

Author(s):

Yonghui Tang

Keyword(s):

High Performance ◽

Phase Locked Loop ◽

Loop Design ◽

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Receiver, Laser Driver, and Phase-Locked Loop Design Issues

Handbook of Fiber Optic Data Communication ◽

10.1016/b978-012207891-0/50018-1 ◽

2002 ◽

pp. 655-674

Author(s):

Dave Siljenberg

Keyword(s):

Phase Locked Loop ◽

Design Issues ◽

Loop Design ◽

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A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL)

Integration ◽

10.1016/j.vlsi.2017.04.001 ◽

2017 ◽

Vol 58 ◽

pp. 142-154 ◽

Author(s):

Yalcin Balcioglu ◽

Gunhan Dundar

Keyword(s):

Phase Locked Loop ◽

Design Analysis ◽

High Level Synthesis ◽

Standard Cell ◽

Loop Design ◽

Synthesis Tool ◽

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Digital phase locked loop design using discrete time sliding mode loop filter

2013 IEEE 9th International Conference on Emerging Technologies (ICET) ◽

10.1109/icet.2013.6743517 ◽

2013 ◽

Author(s):

M. Asad ◽

A. I. Bhatti ◽

S. Iqbal

Keyword(s):

Discrete Time ◽

Sliding Mode ◽

Phase Locked Loop ◽

Loop Filter ◽

Digital Phase ◽

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Jitter optimization based on phase-locked loop design parameters

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ◽

10.1109/isscc.2002.992974 ◽

2003 ◽

Author(s):

M. Mansuri ◽

Chih-Kong Ken Yang

Keyword(s):

Phase Locked Loop ◽

Design Parameters ◽

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Optimal phase-locked loop design with Kalman predictors for synchronous networks

1997 IEEE International Conference on Acoustics, Speech, and Signal Processing ◽

10.1109/icassp.1997.598916 ◽

2002 ◽

Author(s):

G.A. Hirchoren ◽

D.S. Arantes

Keyword(s):

Phase Locked Loop ◽

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