Digital phase locked loop design using discrete time sliding mode loop filter

2013 ◽  
Author(s):  
M. Asad ◽  
A. I. Bhatti ◽  
S. Iqbal
Keyword(s):  
Discrete Time ◽  
Sliding Mode ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Digital Phase ◽  
Loop Design

Adaptive angle tracking loop design based on digital phase-locked loop

2016 ◽  
Vol 125 ◽  
pp. 221-236 ◽  
Author(s):  
Bingbing Jiang ◽  
Weixing Sheng ◽  
Renli Zhang ◽  
Yubing Han ◽  
Xiaofeng Ma
Keyword(s):  
Phase Locked Loop ◽  
Tracking Loop ◽  
Digital Phase ◽  
Loop Design ◽  
Angle Tracking

scholarly journals Design of All Digital Phase Locked Loop for Wireless Applications

2018 ◽  
Vol 7 (3.12) ◽  
pp. 836
Author(s):  
Swetha R ◽  
J Manjula ◽  
A Ruhan bevi
Keyword(s):  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detector ◽  
Ring Oscillator ◽  
Frequency Range ◽  
Loop Filter ◽  
Wireless Applications ◽  
Digital Phase ◽  
Operating Frequency Range

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW. 

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