2021 ◽  
Author(s):  
Zerun Jin ◽  
Zhi-Jian Chen ◽  
Riyan Wang ◽  
Bin Li ◽  
Xiao-Ling Lin

2021 ◽  
Vol 2108 (1) ◽  
pp. 012102
Author(s):  
Chao Ma ◽  
Hongjiang Wu ◽  
Xudong Lu ◽  
Haitao Sun

Abstract Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).


2013 ◽  
Vol 60 (4) ◽  
pp. 192-196 ◽  
Author(s):  
Bogdan Georgescu ◽  
Roghoyeh Salmeh ◽  
Michel Fattouche ◽  
Fadhel Ghannouchi

Sign in / Sign up

Export Citation Format

Share Document