A Dynamic Current Sharing Method in Multi-chip SiC Power Module Using Stacked DBC Bridges and Decoupling Capacitors Based on the Original Simple Module Layout

Author(s):  
Jianwei Lv ◽  
Chi Zhang ◽  
Cai Chen ◽  
Yong Kang
2008 ◽  
Vol 23 (1) ◽  
pp. 206-217 ◽  
Author(s):  
R. Azar ◽  
R. Udrea ◽  
Wai Tung Ng ◽  
F. Dawson ◽  
W. Findlay ◽  
...  

2018 ◽  
Vol 33 (12) ◽  
pp. 10594-10601 ◽  
Author(s):  
Li Yang ◽  
Ke Li ◽  
Jingru Dai ◽  
Martin Corfield ◽  
Anne Harris ◽  
...  

2016 ◽  
Vol 858 ◽  
pp. 1057-1060 ◽  
Author(s):  
Konstantin Kostov ◽  
Jang Kwon Lim ◽  
Ya Fan Zhang ◽  
Mietek Bakowski

The package parasitics are a serious obstacle to the high-speed switching, which is necessary in order to reduce the switching power losses or reduce the size of power converters. In order to design new packages suitable for Silicon Carbide (SiC) power transistors, it is necessary to extract the parasitics of different packages and be able to predict the switching performance of the power devices placed in these packages. This paper presents two ways of simulating the switching performance in a half-bridge power module with SiC MOSFETs. The results show that the parasitic inductances in the power module slow down the switching, lead to poor current sharing, and together with the parasitic capacitances lead to oscillations. These negative effects can cause failures, increased losses, and electromagnetic compatibility issues.


1998 ◽  
Author(s):  
Takatsugu Munehiro ◽  
Kurao Nakagawa ◽  
Junichi Matsuoka ◽  
Hajime Fukui
Keyword(s):  

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