FPGA implementation of iterative decoder for turbo codes for software defined radio

2016 ◽  
Author(s):  
Shivshankar Mishra ◽  
Anjali Mishra ◽  
Anish Shastri ◽  
Suneel Madhekar
Keyword(s):  
Turbo Codes ◽  
Software Defined Radio ◽  
Fpga Implementation ◽  
Iterative Decoder

scholarly journals A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

2011 ◽  
Vol 2011 ◽  
pp. 1-10 ◽  
Author(s):  
Indranil Hatai ◽  
Indrajit Chakrabarti
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Dynamic Range ◽  
Fpga Implementation ◽  
Clock Frequency ◽  
System Clock ◽  
Quarter Wave ◽  
The Individual

This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS) based on quarter-wave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.

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