High speed image acquisition system for 3D reconstruction

This paper introduces a design of a high-speed image acquisition system based on Avalon bus which is supported with SOPC technology. Some peripherals embedded in Avalon bus were customized and utilized in this system, such as imaging unit, decoding unit and storage unit, and these improved the speed of the whole imaging system. The data is compressed to three-fourths of the original by the decoding unit. A custom DMA is designed for moving the image data to the two caches of the SDRAM. This approach discards the method that FIFO must be put up in the traditional data acquisition system. And therefore, it reduced the CPU’s task for data moving. At the same time, the image acquisition and the data transmission can complete a parallel job. Finally, the design is worked on the high-speed image acquisition system which is made up of 2K*2K CMOS image sensor. And it improved the image acquisition speed by three ways: data encoding, custom DMA controller and the parallel processing.

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Image Acquisition System Design of Camera Based on FPGA

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.668-669.836 ◽

2014 ◽

Vol 668-669 ◽

pp. 836-839

Author(s):

Jun Chao Zhu ◽

Yong Chen Li ◽

Ying Kui Jiao ◽

Zhi Jun Ma

Keyword(s):

High Speed ◽

Image Acquisition ◽

Image Sensor ◽

Acquisition System ◽

Ping Pong ◽

Cmos Sensor ◽

Image Acquisition System ◽

High Speed Data ◽

Fpga Chip ◽

Image Collection

It designs an image acquisition system of the camera based on FPGA. It uses a CMOS image sensor as the sensitive chip and controls the timing of image collection by designing the FPGA. FPGA transfers captured image into a PC to display. It uses the I2C bus to initiate CMOS sensor. A problem of cross-clock is solved by asynchronous FIFO. By the ping-pong operation based on two SDRAM chips to solve the problem of high speed data cache. The FPGA chip communicates signal data with PC by Ethernet port. The experiment proved that the system is able to collect 2048×1536 resolution images in a speed of 12fps.

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Visual inspection system for trackside communication and signal infrastructure

Proceedings of the Institution of Mechanical Engineers Part F Journal of Rail and Rapid Transit ◽

10.1177/0954409719899201 ◽

2020 ◽

Vol 235 (1) ◽

pp. 121-130

Author(s):

Xinyu Du ◽

Dan Wu

Keyword(s):

High Speed ◽

Visual Inspection ◽

Image Acquisition ◽

Acquisition System ◽

Gaussian Kernel ◽

Inspection System ◽

Retinex Algorithm ◽

Railway System ◽

Image Acquisition System ◽

Image Details

Trackside communication and signal infrastructure (TCSI) plays an important role in the safe operation of a high-speed railway system. However, it is a challenge to inspect such infrastructure using a vision-based system because of the uneven illumination and various reflection properties of the TCSI surfaces. This paper puts forward a visual inspection system installed on an inspection car for TCSI. The visual inspection system first captures the trackside images using the image acquisition system. Then, an image processing method using a varying-scale Retinex algorithm is implemented so that the visual inspection system can enhance the contrast of these trackside images. The method changes the size of the Gaussian kernel adaptively according to the image details in order to prevent halo artifacts and graying-out effects inherent in many image enhancement algorithms. By comparison with several state of the art methods, varying-scale Retinex is validated to overcome the local inhomogeneous brightness of images and make those images more suitable for browsing and analysis for inspectors. Composed of the image acquisition system and varying-scale Retinex, the visual inspection system is installed on many inspection cars in China for performing visual inspection.

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