Digital Logic Gate Using Quantum-Dot Cellular Automata

Science ◽  
1999 ◽  
Vol 284 (5412) ◽  
pp. 289-291 ◽  
Author(s):  
I. Amlani
2021 ◽  
Author(s):  
Mukesh Patidar ◽  
Namit Gupta

Abstract Quantum-dot cellular automata (QCA) are a novel dominant transistor-less computational nanotechnology. It is an appropriate candidate for the upcoming generation of quantum computational nano-electronics technology. The main objective of this research work is to present a QCA reversible logic circuits design such as the Toffoli gate (TG) and Peres gate (PG) and do the analysis of different parameters. In this paper, we propose a single layer coplanar method to solve this physical layout design and synchronization problem. The presented reversible logic gate (RLG) layout designs are implemented by Bijection functional algorithm for reduction of the number of QCA (quantum) cells, latency, and minimum design area. Also, the Optimized energy dissipation and effect of temperature on output polarization cell, of the proposed structure have been checked successfully using the tool QD-E (Energy) tool. The proposed QCA design has been verified by QCADesigner-E 2.2 tool using a bistable approximation and coherence vector engine. Finally, comparisons have been proposed RLG-TG and RLG-PG designs with the existing QCA design.


2008 ◽  
Vol 47 (6) ◽  
pp. 5000-5006 ◽  
Author(s):  
Primoz Pecar ◽  
Miha Mraz ◽  
Nikolaj Zimic ◽  
Miha Janez ◽  
Iztok Lebar Bajec

2021 ◽  
Vol 11 (24) ◽  
pp. 12157
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar ◽  
Khan A. Wahid

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.


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