CORRELATION BETWEEN PHASE AND AMPLITUDE NOISES, AND 1/F PHASE NOISE REDUCTION METHODS IN OSCILLATORS AND PLL(PHASE-LOCKED LOOP) SYSTEM

Author(s):  
TADASHI YAMOTO ◽  
HARUMITU KANO ◽  
KEIJI TAKAGI
2018 ◽  
Vol 89 (1) ◽  
pp. 013103 ◽  
Author(s):  
C. F. Wu ◽  
X. S. Yan ◽  
J. Q. Huang ◽  
J. W. Zhang ◽  
L. J. Wang

1971 ◽  
Vol 37 (293) ◽  
pp. 203-211
Author(s):  
Aizoh KUBO ◽  
Toshiaki ANDO ◽  
Susumu SATO ◽  
Toshio AIDA ◽  
Takeshi HOSHIRO

2020 ◽  
Vol 4 (67) ◽  
pp. 153-160
Author(s):  
Oleg I. Polivaev ◽  
◽  
Alexey N. Kuznetsov ◽  
Dmitriy Yu. Terekhov ◽  
Viktor V. Trufanov ◽  
...  

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.


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