Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

scholarly journals A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-8 ◽  
Author(s):  
Tzung-Je Lee ◽  
Chua-Chin Wang
Keyword(s):  
Power Consumption ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Supply Noise

A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled.

scholarly journals A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

Sensors ◽  
2021 ◽  
Vol 21 (22) ◽  
pp. 7648
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Phase Noise ◽  
Root Mean Square ◽  
Supply Voltage ◽  
Cmos Process ◽  
Type I ◽  
Voltage Controlled Oscillator ◽  
Mean Square ◽  
Frequency Range ◽  
Output Frequency ◽  
Zero Phase

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and −251.6 dB FoM.

scholarly journals Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 504
Author(s):  
Ranran Zhao ◽  
Yuming Zhang ◽  
Hongliang Lv ◽  
Yue Wu
Keyword(s):  
Maximum Output Power ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Signal Frequency ◽  
Maximum Output ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Frequency Source ◽  
A Charge

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

IMPLEMENTATION OF AN RF CMOS QUADRATURE LC VOLTAGE-CONTROLLED OSCILLATOR BASED ON THE SWITCHED TAIL TRANSISTOR TOPOLOGY

2010 ◽  
Vol 19 (05) ◽  
pp. 931-937
Author(s):  
APINUNT THANACHAYANONT ◽  
MONAI KRAIRIKSH
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Coupling Mechanism ◽  
Voltage Controlled Oscillator ◽  
Rf Cmos ◽  
Power Supply Voltage ◽  
Switch Capacitor ◽  
Measurement Results ◽  
Offset Frequency ◽  
Signal Swing

This paper describes the design and implementation of an RF CMOS quadrature LC voltage-controlled oscillator in a 0.35 μm technology. The proposed oscillator employs the switched tail transistor topology and differential switch capacitor tuning to achieve low phase noise operation. A modified series coupling mechanism is used for quadrature signal generation with wide output signal swing. The oscillator core circuit was designed to operate with a 2.5 V power supply voltage with a 4 mA total supply current. Measurement results showed that the prototype oscillator could achieve a nominal oscillation frequency of 2.2 GHz with -110 dBc/Hz phase noise at 1 MHz offset frequency.

scholarly journals A Low Power Voltage Controlled Oscillator Design

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Manoj Kumar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Nand Gate ◽  
Frequency Variation ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Voltage Controlled Oscillators ◽  
Delay Cell ◽  
Voltage Variation

The performance of voltage controlled oscillator (VCO) is of great importance for any telecommunication or data transmission network. Here, voltage controlled oscillators (VCOs) using three-transistor NAND gates have been designed. New delay cell with three-transistor NAND gate has been used for designing the ring based VCO circuits. Three-, five-, and seven-stage VCOs have been proposed. Output frequency has been controlled with supply voltage variation from 1.8 V to 2.4 V. Three stage VCO shows output frequency variation in the range of 3.2909 GHz to 4.2280 GHz whereas power consumption varies in the range of 335.4071 μW to 486.1816 μW. Five-stage VCO depicts frequency in the range of 1.9406 GHz to 2.5769 GHz with power consumption variation from 559.0118 μW to 810.3027 μW. Moreover a seven-stage VCO shows frequency variation from 1.3984 GHz to 1.8077 GHz. Power consumption of seven-stage VCO varies from 782.6165 μW to 1134.400 μW. Phase noise results for these VCOs have also been obtained. Power consumption, output frequency, and phase noise results of proposed circuits have been compared with earlier reported circuits, and the proposed circuits show significant improvements.

scholarly journals PLL DESIGN AND INVESTIGATION IN CMOS

2010 ◽  
Vol 2 (1) ◽  
pp. 54-58
Author(s):  
Jevgenij Charlamov
Keyword(s):  
Phase Noise ◽  
Noise Analysis ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Functional Blocks ◽  
Oscillator Phase Noise ◽  
A Charge ◽  
The Relationship ◽  
Oscillator Phase

In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 1010-1013
Author(s):  
Tsung Han Han ◽  
Meng Ting Hsu ◽  
Cheng Chuan Chung
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Voltage Controlled Oscillators ◽  
Communication Circuits ◽  
5 Ghz ◽  
Low Phase Noise

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz–6.1 GHz Applications in 0.18 μm CMOS

2019 ◽  
Vol 28 (11) ◽  
pp. 1950182 ◽  
Author(s):  
Nitin Kumar ◽  
Manoj Kumar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Control Voltage ◽  
Cmos Process ◽  
Output Frequency ◽  
Differential Ring ◽  
Low Phase Noise ◽  
High Output

The differential ring voltage controlled oscillator (VCO) is one of the critical devices in wireless communication system having excellent stability, controllability and noise rejection ability. A novel design of delay cell is proposed for the four staged CMOS differential ring VCO with high output frequency, low power consumption and low phase noise. The differential ring VCO utilizes multiloop dual delay path topology to acquire both high output frequency and low phase noise. Results have been achieved in TSMC 0.18-[Formula: see text]m CMOS process with a supply voltage ([Formula: see text]) 1.8[Formula: see text]V. The proposed design achieves an output frequency range of 4.029[Formula: see text]GHz to 6.122[Formula: see text]GHz and power of 4.475[Formula: see text]mW is consumed with control voltage variation from 1[Formula: see text]V to 2[Formula: see text]V. The proposed VCO exhibits [Formula: see text]89.7[Formula: see text]dBc/Hz phase noise at 1[Formula: see text]MHz offset frequency and the corresponding figure of merit (FoM) is [Formula: see text]155.9[Formula: see text]dBc/Hz. The design of differential ring VCO with novel delay stage has improved performance in terms of power consumption, output oscillation frequency and phase noise.

A Low Phase Noise Fully Monolithic 6 GHz Differential Coupled NMOS LC-VCO

Frequenz ◽  
2016 ◽  
Vol 70 (1-2) ◽  
Author(s):  
Dorra Mellouli Moalla ◽  
David Cordeau ◽  
Hassene Mnif ◽  
Jean-Marie Paillot ◽  
Mourad Loulou
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Supply Voltage ◽  
Worst Case ◽  
Resistive Network ◽  
Phased Antenna Array ◽  
Free Running ◽  
Phase Progression ◽  
Low Phase Noise

AbstractA fully monolithic 6 GHz low-phase noise Voltage-Controlled-Oscillator (VCO) is presented in this paper. It consists in two LC-NMOS differential VCOs coupled through a resistive network and is implemented on a 0.25 µm BiCMOS SiGe process. This proposed integrated VCO can be used also for phased-array applications to steer the beam over the entire spatial range. In this case, the radiation pattern of the phased antenna array is steered in a particular direction by establishing a constant phase progression in the oscillator chain which can be obtained by detuning the free-running frequencies of the two oscillators in the array. At 2.5 V power supply voltage and a power dissipation of 62.5 mW, the coupled VCO array features a measured worst case phase noise of

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