Bus Optimization for Low Power in High-Level Synthesis

2003 ◽  
Vol 12 (01) ◽  
pp. 1-17
Author(s):  
Sungpack Hong ◽  
Taewhan Kim
Keyword(s):  
Optimal Solution ◽  
Minimum Cost ◽  
Maximum Flow ◽  
High Level Synthesis ◽  
Benchmark Problems ◽  
Timing Constraints ◽  
Power Efficient ◽  
High Level ◽  
The Impact ◽  
Operation Scheduling

Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and the RT level of design. This paper addresses the problem of minimizing power dissipated in the switching of the buses in the high-level synthesis of data-dominated behavioral descriptions. Unlike the previous approaches in which the minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on the reduction of power dissipated on the buses more fully and effectively. We accomplish this by formulating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds the maximum flow of minimum cost solutions in the network. Experimental results on a number of benchmark problems show that given resource and global timing constraints our designs are 19.8% power-efficient over the designs produced by a random-move based solution, and 15.5% power-efficient over the designs by a clock-step based optimal solution.

scholarly journals Power Efficient Rapid Design Space Exploration of Integrated Scheduling and Module Selection in High Level Synthesis

2021 ◽  
Author(s):  
Pallabi Sarkar
Keyword(s):  
Power Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
Optimal Solutions ◽  
Power Efficient ◽  
Pi Method ◽  
High Level

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

scholarly journals Optimization of open flow controller placement in software defined networks

2021 ◽  
Vol 11 (4) ◽  
pp. 3145
Author(s):  
Raghda Salam Al mahdawi ◽  
Huda M. Salih
Keyword(s):  
Network Architecture ◽  
Optimal Solution ◽  
Minimum Cost ◽  
Open Flow ◽  
Processing Power ◽  
Input Size ◽  
Different Types ◽  
Network Topologies ◽  
High Level ◽  
The Cost

The world is entering into the era of Big Data where computer networks are an essential part. However, the current network architecture is not very convenient to configure such leap. Software defined network (SDN) is a new network architecture which argues the separation of control and data planes of the network devices by centralizing the former in high level, centralised devices and efficient supervisors, called controllers. This paper proposes a mathematical model that helps optimizing the locations of the controllers within the network while minimizing the overall cost under realistic constrains. Our method includes finding the minimum cost of placing the controllers; these costs are the network latency, controller processing power and link bandwidth. Different types of network topologies have been adopted to consider the data profile of the controllers, links of controllers and locations of switches. The results showed that as the size of input data increased, the time to find the optimal solution also increased in a non-polynomial time. In addition, the cost of solution is increased linearly with the input size. Furthermore, when increasing allocating possible locations of the controllers, for the same number of switches, the cost was found to be less.

scholarly journals Power Efficient Rapid Design Space Exploration of Integrated Scheduling and Module Selection in High Level Synthesis

2021 ◽  
Author(s):  
Pallabi Sarkar
Keyword(s):  
Power Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
Optimal Solutions ◽  
Power Efficient ◽  
Pi Method ◽  
High Level

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

"Energy Cost Calculations for Enhanced Power Efficient Gathering in Sensor Information Systems Algorithm with Mobile-Sink "

2021 ◽  
Vol 8 (1) ◽  
pp. 14-21
Author(s):  
"Mohammad Kh. R. Al-juaifari
Keyword(s):  
Information Systems ◽  
Network Performance ◽  
Data Transfer ◽  
Data Gathering ◽  
Minimum Cost ◽  
Life Time ◽  
Mobile Sink ◽  
Power Efficient ◽  
Sensor Information ◽  
The Impact

"The issue of energy consumption in wireless sensor networks is an important issue nowadays, Power efficient gathering in sensor information systems (PEGASIS) acts as routing protocols improve the energy consumed, which is one of the most important hierarchical directives used and that works to collect and transfer data to and from a neighbor to reduce duplication of data transfer by transferring data to bypass the dead node. In this research paper, experimental results have been made to improve the performance with new location for nodes trajectory to mobile sink, Finally, minimum cost for data gathering calculated to optimize network performance and life time with parameters of enhanced PEGASIS criteria to show the impact of factors changing.

scholarly journals A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
D. S. Harish Ram ◽  
M. C. Bhuvaneswari ◽  
Shanthi S. Prabhu
Keyword(s):  
High Level Synthesis ◽  
Synthesis Process ◽  
Weighted Sum ◽  
Early Assessment ◽  
Nsga Ii ◽  
Multi Objective ◽  
Trade Offs ◽  
Evolutionary Technique ◽  
High Level ◽  
The Impact

High-Level Synthesis deals with the translation of algorithmic descriptions into an RTL implementation. It is highly multi-objective in nature, necessitating trade-offs between mutually conflicting objectives such as area, power and delay. Thus design space exploration is integral to the High Level Synthesis process for early assessment of the impact of these trade-offs. We propose a methodology for multi-objective optimization of Area, Power and Delay during High Level Synthesis of data paths from Data Flow Graphs (DFGs). The technique performs scheduling and allocation of functional units and registers concurrently. A novel metric based technique is incorporated into the algorithm to estimate the likelihood of a schedule to yield low-power solutions. A true multi-objective evolutionary technique, “Nondominated Sorting Genetic Algorithm II” (NSGA II) is used in this work. Results on standard DFG benchmarks indicate that the NSGA II based approach is much faster than a weighted sum GA approach. It also yields superior solutions in terms of diversity and closeness to the true Pareto front. In addition a framework for applying another evolutionary technique: Weighted Sum Particle Swarm Optimization (WSPSO) is also reported. It is observed that compared to WSGA, WSPSO shows considerable improvement in execution time with comparable solution quality.

scholarly journals High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

2011 ◽  
Vol 2011 ◽  
pp. 1-17 ◽  
Author(s):  
John Curreri ◽  
Greg Stitt ◽  
Alan D. George
Keyword(s):  
Timing Analysis ◽  
High Level Synthesis ◽  
Timing Constraints ◽  
Software Developers ◽  
Design Complexity ◽  
Elapsed Time ◽  
Area Overhead ◽  
Limited Support ◽  
Significant Performance ◽  
High Level

Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy register-transfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

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