THEORETICAL AND EXPERIMENTAL EVALUATION OF THE PHASE NOISE BEHAVIOR OF A DUAL-LOOP FREQUENCY SYNTHESIZER FOR 5-GHz WLANs

This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high-frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution, and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimization of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration.