SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940010
Author(s):  
Petr Fišer ◽  
Ivo Háleček ◽  
Jan Schmidt ◽  
Václav Šimek

This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one or enumerate all optimum implementations, while the allowed target gate types and gates costs can be arbitrarily specified. Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable of performing two or more different intended functions, depending on instantaneous conditions in the target operating environment. In this paper we propose the first method ever, generating provably size-optimal polymorphic circuits. Scalability and feasibility of the method are documented by providing experimental results for all NPN-equivalence classes of four-input functions implemented in AND–Inverter and AND–XOR–Inverter logics without polymorphic behavior support being used and for all pairs of NPN–equivalence classes of three-input functions for polymorphic circuits. Finally, several smaller benchmark circuits were synthesized optimally, both in standard and polymorphic logics.

2010 ◽  
Vol 7 (1) ◽  
pp. 189-200 ◽  
Author(s):  
Haitao Wei ◽  
Yu Junqing ◽  
Li Jiang

As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates four level parallelisms - frame-level, slice-level, macroblock-level and data-level into one implementation. Each level parallelism is designed in a hierarchical parallel framework and mapped onto the multi-cores and SIMD units on multi-core architecture. According to the analysis of coding performance on each level parallelism, we propose a method to combine different parallel levels to attain a good compromise between high speedup and low bit-rate. The experimental results show that for CIF format video, our method achieves the speedup of 33.57x-42.3x with 1.04x-1.08x bit-rate increasing on 8-core Intel Xeon processor with SIMD Technology.


1996 ◽  
Vol 14 (4) ◽  
pp. 263-312 ◽  
Author(s):  
W.K. Chow

Two fire zone models CFAST 2.0 and BRI2T are applied to simulate fires in multi-level apartments. Apartments with different levels and several compartments including a staircase are taken as examples. Smoke con trol designs including ceiling vents and smoke extraction systems installed in the staircase are considered with their performance evaluated. Experimental results reported in the literature are used to compare with the predicted results.


2021 ◽  
Vol 31 (02) ◽  
pp. 2150031
Author(s):  
Qinbin He ◽  
Fangyue Chen ◽  
Wei Jin

The concept of conformal transformation is proposed through the study of the spatial structure of [Formula: see text]-dimensional hypercubes. Based on conformal transformation, a novel algorithm, called topological equivalence classification algorithm, is proposed for classifying balanced linearly separable Boolean functions. By the proposed algorithm, the topological equivalence classes of all balanced linearly separable Boolean functions and the number of Boolean functions in each of the topological equivalence classes are obtained. In addition, the properties of conformal transformation also show an application prospect for decomposing nonlinearly separable Boolean functions.


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