A network combining packet switching and time division circuit switching in a common system

1976 ◽  
Vol 6 (1) ◽  
pp. 38-62 ◽  
Author(s):  
Joe de Smet ◽  
Ray W. Sanders
Keyword(s):  
Packet Switching ◽  
Circuit Switching ◽  
Common System ◽  
Time Division

scholarly journals Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

2012 ◽  
Vol 2012 ◽  
pp. 1-16 ◽  
Author(s):  
Angelo Kuti Lusala ◽  
Jean-Didier Legat
Keyword(s):  
Packet Switching ◽  
Circuit Switching ◽  
Path Diversity ◽  
Best Effort ◽  
Networks On Chip ◽  
Streaming Traffic ◽  
On Chip ◽  
Time Division ◽  
Spatial Division Multiplexing ◽  
Best Effort Traffic

A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Multiplexing “TDM” technique in the circuit switching part in order to increase path diversity, thus improving throughput while sharing communication resources among multiple connections. Combining these two techniques allows mitigating the poor resource usage inherent to circuit switching. In this way Quality of Service “QoS” is easily provided for the streaming traffic through the circuit-switched sub-router while the packet-switched sub-router handles best-effort traffic. The proposed hybrid router architectures were synthesized, placed and routed on an FPGA. Results show that a practicable Network-on-Chip “NoC” can be built using the proposed router architectures. 7 × 7 mesh NoCs were simulated in SystemC. Simulation results show that the probability of establishing paths through the NoC increases with the number of sub-channels and has its highest value when combining SDM with TDM, thereby significantly reducing contention in the NoC.

Optical Burst Switching

2011 ◽  
pp. 799-806
Author(s):  
Joel J.P.C. Rodrigues ◽  
Paulo P. Monteiro ◽  
Pascal Lorenz
Keyword(s):  
Packet Switching ◽  
Optical Burst Switching ◽  
Optical Packet Switching ◽  
Destination Node ◽  
Time Interval ◽  
Circuit Switching ◽  
Burst Switching ◽  
Data Control ◽  
Optical Buffering ◽  
Optical Burst

The concept of burst switching was proposed initially in the context of voice communications by Haselton (1983) and Amstutz (1983; 1989) in the early 1980s. More recently, in the late 1990s, optical burst switching (OBS) was proposed as a new switching paradigm for the so-called optical Internet in order to overcome the technical limitations of optical packet switching; namely, the lack of optical random access memory (optical RAM) and to the problems with synchronization.(Yoo & Qiao, 1997; Qiao & Yoo, 1999; Chen, Qiao & Yu, 2004; Turner, 1999; Baldine, Rouskas, Perros & Stevenson, 2002; Xu, Perros & Rouskas, 2001). OBS is a technical compromise between wavelength routing and optical packet switching, since it does not require optical buffering or packet-level processing as in optical packet switching, and it is more efficient than circuit switching if the traffic volume does not require a full wavelength channel. According to Dolzer, Gauger, Späth, and Bodamer (2001), OBS has the following characteristics: • Granularity: The transmission unit size (burst) of OBS is between the optical circuit switching and optical packet switching. • Separation Between Control and Data: Control information (header) and data are transmitted on different wavelengths (or channels) with some time interval. • Allocation of Resources: Resources are allocated using mainly one-way reservation schemes. A source node does not need to wait for the acknowledge message from destination node to start transmitting the burst. • Variable Burst Length: The burst size is variable. • No Optical Buffering: Burst switching does not require optical buffering at the intermediate nodes (without any delay).

scholarly journals A New Router Architecture for High-Performance Intrachip Networks

2008 ◽  
Vol 3 (1) ◽  
pp. 23-31
Author(s):  
Everton Carara ◽  
Ney Calazans ◽  
Fernando Moraes
Keyword(s):  
High Performance ◽  
Packet Switching ◽  
Circuit Switching ◽  
Transmission Method ◽  
Communication Architecture ◽  
Virtual Channels ◽  
Trade Offs ◽  
Communication Architectures ◽  
Session Layer ◽  
On Chip

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

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