Designing SPI to I2C Protocol Converter Base on ASIC Technology and Implementing on the FPGA Platform

Nowadays embedded systems are using a lot of different communication standards to transfer data such as USB, UART, SPI, I2C, etc. To be able to transfer data with each communication standard, the system needs at least one controller block for that communication standard. This has added to the complexity of the system and the cost of manufacturing hardware. Embedded systems only support SPI communication if desired, which can still be communicated with peripherals with I2C standard. However, the SPI cannot be directly connected to the I2C but must use a standard communication converter. This paper will primarily focus on designing an IP core communication standard converter from SPI to I2C using APB (Advanced Peripheral Bus) communication as one of the AMBA (Advanced Microcontroller Bus Architecture) communication sets. In particular, APB is a bus used to communicate with peripherals that do not require fast processing speeds such as UART, SPI, I2C, etc.

A comprehensive review of distributed power system architecture for telecom and datacenter applications

With the dominating utility of the internet, it becomes critical to manage the efficiency and reliability of telecom and datacenter, as the power consumption of the involved equipment also increases. Much power being wasted through the power conversion stages by converting AC voltage to DC voltage and then stepping down to lower voltages to connect to information and communication technology (ICT) equipment. 48/12 VDC is the standard DC bus architecture to serve the end utility equipment. This voltage level is further processed to multiple lower voltages to power up the internal auxiliary circuits. Power losses are involved when it is converted from higher voltage to lower voltages. Therefore, the efficiency of power conversion is lower. There is a need to increase the efficiency by minimizing the power losses which occur due to the conversion stages. Different methods are available to increase the efficiency of a system by optimizing the converter topologies, semiconductor materials and control methods. There is another possibility of increasing the efficiency by changing the architecture of a system by increasing the DC bus voltage to higher voltages to optimize the losses. This paper presents a review of available high voltage options for telecom power distribution and developments, implementations and challenges across the world.

Thiết kế và thi công bộ truyền nhận theo giao thức I2C

I2C (Inter-Integrated Circuit) là một chuẩn truyền dữ liệu nối tiếp đồng bộ được sử dụng rộng rãi để kết nối nhiều IC (Integrated Circuit) với nhau hay kết nối các IC và các ngoại vi với tốc độ trung bình thấp trong các hệ thống số. Điểm mạnh của chuẩn I2C là khả năng kết nối giữa vi xử lý trung tâm và nhiều ngoại vi với phần cứng đơn giản. Trong nội dung bài báo này, chúng tôi trình bày quá trình thiết kế một module I2C giao tiếp qua chuẩn bus AMBA APB (Advanced Microcontroller Bus Architecture - Advanced Peripheral Bus). Cụ thể, module I2C được thiết kế bằng ngôn ngữ mô tả phần cứng Verilog, có thể cấu hình là Master hoặc Slave và hỗ trợ nhiều tốc độ truyền dữ liệu khác nhau. Nhiều kết quả đánh giá qua mô phỏng được trình bày để xác thực chất lượng của module I2C được thiết kế.

Electric Power Transfer Concept for Enhanced Performance of the More Electric Engine

In future electrified aircraft, multi-spool more electric engines (MEEs) are expected to be equipped with electric generators connected to each shaft for power offtake and supplying onboard electrical loads. These can be interfaced to a common high-voltage DC bus architecture via power electronic converters. Such system architecture enables the establishment of an "electrical bridge" to circulate the desired amount of power between the engine shafts, and decouple their speeds. This paper introduces the possible benefits from the Electric Power Transfer (EPT) for engine performance and scrutinizes a novel EPT-Adopted Design (EPTAD) for future MEEs. For this purpose, a 0-dimensional engine model has been developed by using the inter-component-volume (ICV) method. By using the engine model, the CFM56-3 engine is redesigned to realize the EPTAD. Comparing the simulation results for the EPTAD and baseline CFM56-3 engines shows significant improvement for engine performance in terms of SFC and surge margin, mainly at cruise condition. Results show that almost 3.2% and 2.2% of fuel burn reduction is achieved for the short- and medium-haul flights respectively, with a 1150 kW EPT system. It is also shown that Variable Bleed Valves (VBVs) can be eliminated in the EPTAD engine with a 1150 kW EPT system.