Activity and register placement aware gated clock network design

2008 ◽  
Author(s):  
Weixiang Shen ◽  
Yici Cai ◽  
Xianlong Hong ◽  
Jiang Hu
Keyword(s):  
Network Design ◽  
Clock Network ◽  
Gated Clock

scholarly journals Low Power Clock Network Design

2011 ◽  
Vol 1 (1) ◽  
pp. 219-246 ◽  
Author(s):  
Inna Vaisband ◽  
Eby G. Friedman ◽  
Ran Ginosar ◽  
Avinoam Kolodny
Keyword(s):  
Low Power ◽  
Network Design ◽  
Clock Network

Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits

2012 ◽  
Vol 31 (8) ◽  
pp. 1222-1234 ◽  
Author(s):  
Xin Zhao ◽  
Jeremy R. Tolbert ◽  
Saibal Mukhopadhyay ◽  
Sung Kyu Lim
Keyword(s):  
Network Design ◽  
Design Methodology ◽  
Clock Network

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

2003 ◽  
Vol 38 (3) ◽  
pp. 457-463 ◽  
Author(s):  
Xuejue Huang ◽  
P. Restle ◽  
T. Bucelot ◽  
Yu Cao ◽  
Tsu-Jae King ◽  
...  
Keyword(s):  
Network Design ◽  
Optimization Approach ◽  
Modeling And Optimization ◽  
Clock Network ◽  
Interconnect Modeling
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