Variation-tolerant and low-power clock network design for 3D ICs

2011 IEEE 61st Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2011.5898792 ◽

2011 ◽

Author(s):

Xin Zhao ◽

Saibal Mukhopadhyay ◽

Sung Kyu Lim

Keyword(s):

Low Power ◽

Network Design ◽

3D Ics ◽

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Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

IEEE Transactions on Components Packaging and Manufacturing Technology ◽

10.1109/tcpmt.2010.2099590 ◽

2011 ◽

Vol 1 (2) ◽

pp. 247-259 ◽

Author(s):

Xin Zhao ◽

Jacob Minz ◽

Sung Kyu Lim

Keyword(s):

Low Power ◽

Network Design ◽

Through Silicon Via ◽

3D Ics ◽

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Low Power Clock Network Design

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea1010219 ◽

2011 ◽

Vol 1 (1) ◽

pp. 219-246 ◽

Author(s):

Inna Vaisband ◽

Eby G. Friedman ◽

Ran Ginosar ◽

Avinoam Kolodny

Keyword(s):

Low Power ◽

Network Design ◽

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Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419900 ◽

2010 ◽

Author(s):

Xin Zhao ◽

Sung Kyu Lim

Keyword(s):

Network Design ◽

Through Silicon Via ◽

3D Ics ◽

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TSV array utilization in low-power 3D clock network design

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design - ISLPED '12 ◽

10.1145/2333660.2333668 ◽

2012 ◽

Author(s):

Xin Zhao ◽

Sung Kyu Lim

Keyword(s):

Low Power ◽

Network Design ◽

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Clock network design techniques for 3D ICs

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2011.6026427 ◽

2011 ◽

Author(s):

Tak-Yung Kim ◽

Taewhan Kim

Keyword(s):

Network Design ◽

3D Ics ◽

Clock Network ◽

Design Techniques

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Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip

Power Aware Design Methodologies ◽

10.1007/0-306-48139-1_6 ◽

2006 ◽

pp. 151-179

Author(s):

Chulwoo Kim ◽

Sung-Mo Steve Kang

Keyword(s):

Low Power ◽

Network Design ◽

High Performance ◽

Flip Flop ◽

Design Methodologies ◽

Clock Network ◽

Performance System ◽

System On A Chip

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Navigating Register Placement for Low Power Clock Network Design

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1093/ietfec/e88-a.12.3405 ◽

2005 ◽

Vol E88-A (12) ◽

pp. 3405-3411 ◽

Author(s):

Y. LU

Keyword(s):

Low Power ◽

Network Design ◽

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Clock network design for ultra-low power applications

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design - ISLPED '10 ◽

10.1145/1840845.1840901 ◽

2010 ◽

Author(s):

Mingoo Seok ◽

David Blaauw ◽

Dennis Sylvester

Keyword(s):

Low Power ◽

Network Design ◽

Ultra Low Power ◽

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A Military Mobile Network Design: mHealth, IoT and Low Power Wide Area Networks

2020 30th International Telecommunication Networks and Applications Conference (ITNAC) ◽

10.1109/itnac50341.2020.9315168 ◽

2020 ◽

Author(s):

James Jin Kang

Keyword(s):

Low Power ◽

Network Design ◽

Mobile Network ◽

Wide Area ◽

Wide Area Networks

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Low Temperature Poly-Si Junctionless TFTs with Low Temperature Cyclic Trimming Process for 3D-ICs and Low Power Applications

10.7567/ssdm.2019.g-4-03 ◽

2019 ◽

Author(s):

C.C-C. Chung ◽

C.M. Ko ◽

T.S. Chao

Keyword(s):

Low Temperature ◽

Low Power ◽

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