High-performance timing simulation of embedded software

Author(s):  
Jürgen Schnerr ◽  
Oliver Bringmann ◽  
Alexander Viehl ◽  
Wolfgang Rosenstiel
2021 ◽  
Author(s):  
Giulia Acconcia ◽  
Francesco Malanga ◽  
Ivan Labanca ◽  
Massimo Ghioni ◽  
Ivan Rech

Author(s):  
Christos Baloukas ◽  
Marijn Temmerman ◽  
Anne Keller ◽  
Stylianos Mamagkakis ◽  
Francky Catthoor ◽  
...  

An embedded system is a special-purpose system that performs predefined tasks, usually with very specific requirements. Since the system is dedicated to a specific task, design engineers can optimize it by exploiting very specialized knowledge, deriving an optimally customized system. Low energy consumption and high performance are both valid optimization targets to increase the value and mobility of the final system. Traditionally, conceptual embedded software models are built irrespectively of the underlying hardware platform, whereas embedded-system specialists typically start their optimization crusade from the executable code. This practice results in suboptimal implementations on the embedded platform because at the source-code level not all the inefficiencies introduced at the modelling level can be removed. In this book chapter, we describe both novel UML transformations at the modelling level and C/C++ transformations at the software implementation level. The transformations at both design abstraction levels target the data types of dynamic embedded software applications and provide optimizations guided by the relevant cost factors. Using a real life case study, we show how our transformations result in significant improvement in memory footprint, performance and energy consumption with respect to the initial implementation. Moreover, thanks to our holistic approach, we are able to identify new and non-trivial solutions that could hardly be found with the traditional design methods.


VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-6 ◽  
Author(s):  
Péter Szántó ◽  
Gábor Szedő ◽  
Béla Fehér

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.


2013 ◽  
Vol 46 (21) ◽  
pp. 249-253
Author(s):  
Marius Rosu ◽  
Vincent Delafosse ◽  
Takayuki Sekisue ◽  
Thierry Le Sergent

1981 ◽  
Vol 180 (2-3) ◽  
pp. 603-614 ◽  
Author(s):  
Gary H. Sanders ◽  
Gregory W. Hart ◽  
Gary E. Hogan ◽  
James S. Frank ◽  
Cyrus M. Hoffman ◽  
...  

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