Field-split parallel architecture for high performance multi-match packet classification using FPGAs

Author(s):  
Weirong Jiang ◽  
Viktor K. Prasanna
MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 5-6
Author(s):  
Horst D. Simon

Recent events in the high-performance computing industry have concerned scientists and the general public regarding a crisis or a lack of leadership in the field. That concern is understandable considering the industry's history from 1993 to 1996. Cray Research, the historic leader in supercomputing technology, was unable to survive financially as an independent company and was acquired by Silicon Graphics. Two ambitious new companies that introduced new technologies in the late 1980s and early 1990s—Thinking Machines and Kendall Square Research—were commercial failures and went out of business. And Intel, which introduced its Paragon supercomputer in 1994, discontinued production only two years later.During the same time frame, scientists who had finished the laborious task of writing scientific codes to run on vector parallel supercomputers learned that those codes would have to be rewritten if they were to run on the next-generation, highly parallel architecture. Scientists who are not yet involved in high-performance computing are understandably hesitant about committing their time and energy to such an apparently unstable enterprise.However, beneath the commercial chaos of the last several years, a technological revolution has been occurring. The good news is that the revolution is over, leading to five to ten years of predictable stability, steady improvements in system performance, and increased productivity for scientific applications. It is time for scientists who were sitting on the fence to jump in and reap the benefits of the new technology.


1991 ◽  
Author(s):  
Eric A. Brewer ◽  
Chrysanthos N. Dellarocas ◽  
Adrian Colbrook ◽  
William E. Weihl

1994 ◽  
Vol 6 (2) ◽  
pp. 131-136
Author(s):  
Yoshifumi Sasaki ◽  
◽  
Michitaka Kameyama

For intelligent robots, a robot vision system is usually required to perform three-dimensional (3-D) position estimation as well as object recognition at high speeds. In this paper, we propose an algorithm for 3-D object recognition and position estimation for the implementation of a VLSI processor The principle of the algorithm is based on model matching between an input image and models stored in memory. Because of enormous computation time, the development of a high-performance VLSI processor is essential. Highly parallel architecture is introduced in the VLSI processor to reduce the latency. As a result of highly parallel computing, the computational time is 10000 times faster than that of a 28.5 MIPS workstation.


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