High Performance Computational Hydrodynamic Simulations: UPC Parallel Architecture as a Future Alternative

2018 ◽  
pp. 444-455 ◽  
Author(s):  
Alvin Wei Ze Chew ◽  
Tung Thanh Vu ◽  
Adrian Wing-Keung Law
Keyword(s):  
High Performance ◽  
Parallel Architecture ◽  
Hydrodynamic Simulations

The Recent Revolution in High Performance Computing

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 5-6
Author(s):  
Horst D. Simon
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
New Technologies ◽  
New Technology ◽  
Parallel Architecture ◽  
Time Frame ◽  
Good News ◽  
Computing Industry ◽  
Time And Energy ◽  
Performance Computing

Recent events in the high-performance computing industry have concerned scientists and the general public regarding a crisis or a lack of leadership in the field. That concern is understandable considering the industry's history from 1993 to 1996. Cray Research, the historic leader in supercomputing technology, was unable to survive financially as an independent company and was acquired by Silicon Graphics. Two ambitious new companies that introduced new technologies in the late 1980s and early 1990s—Thinking Machines and Kendall Square Research—were commercial failures and went out of business. And Intel, which introduced its Paragon supercomputer in 1994, discontinued production only two years later.During the same time frame, scientists who had finished the laborious task of writing scientific codes to run on vector parallel supercomputers learned that those codes would have to be rewritten if they were to run on the next-generation, highly parallel architecture. Scientists who are not yet involved in high-performance computing are understandably hesitant about committing their time and energy to such an apparently unstable enterprise.However, beneath the commercial chaos of the last several years, a technological revolution has been occurring. The good news is that the revolution is over, leading to five to ten years of predictable stability, steady improvements in system performance, and increased productivity for scientific applications. It is time for scientists who were sitting on the fence to jump in and reap the benefits of the new technology.

PROTEUS: A High-Performance Parallel-Architecture Simulator

1991 ◽  
Author(s):  
Eric A. Brewer ◽  
Chrysanthos N. Dellarocas ◽  
Adrian Colbrook ◽  
William E. Weihl
Keyword(s):  
High Performance ◽  
Parallel Architecture

3D Stacks of Microprocessors and Memories With Backside Two-Phase Multi-Microchannel Cooler

2013 ◽  
Author(s):  
Jackson B. Marcinichen ◽  
John R. Thome
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Flow Distribution ◽  
Two Phase ◽  
Hydrodynamic Simulations ◽  
3D Ics ◽  
Technological Advances ◽  
High Level ◽  
Transfer Of Information ◽  
High Performance Computers

For the next generation of high performance computers, the new challenges are to shorten the distance for transporting data (to accelerate the transfer of information) between multi-microprocessors and memories, and to cool these electronic components despite the increased heat flux that results from increased transistor density. Recent technological advances show a tendency for the development of 3D integrated circuit stacked architectures with interlayer cooling (multi-microchannels in the silicon layers). However, huge challenges exist in such design/concept, i.e. flow distribution to hundreds microchannels distributed in the different interlayers, thermo-hydrodynamic and geometrical limitations, manufacturing etc. 3D-ICs with interlayer cooling are still about a decade away, so a viable shorter term goal is 3D stacks with backside cooling, taking advantage of Si layers now able to be thineer down to only 50 μm thickness. Thus, the present work presents thermo-hydrodynamic simulations for 3D stacks considering only a backside cooler, which simplifies considerably the assembly and guarantees a high level of reliability. In summary, the results showed that this concept is thermally feasible and potentially that interlayer microchannels (between stacks) will not be necessary.

Design of a Model-Based Robot Vision VLSI Processor

1994 ◽  
Vol 6 (2) ◽  
pp. 131-136
Author(s):  
Yoshifumi Sasaki ◽  
◽  
Michitaka Kameyama
Keyword(s):  
Object Recognition ◽  
High Performance ◽  
Vision System ◽  
Robot Vision ◽  
Parallel Architecture ◽  
Computation Time ◽  
Input Image ◽  
Position Estimation ◽  
Computational Time ◽  
Model Matching

For intelligent robots, a robot vision system is usually required to perform three-dimensional (3-D) position estimation as well as object recognition at high speeds. In this paper, we propose an algorithm for 3-D object recognition and position estimation for the implementation of a VLSI processor The principle of the algorithm is based on model matching between an input image and models stored in memory. Because of enormous computation time, the development of a high-performance VLSI processor is essential. Highly parallel architecture is introduced in the VLSI processor to reduce the latency. As a result of highly parallel computing, the computational time is 10000 times faster than that of a 28.5 MIPS workstation.

scholarly journals An Optimal Implementation on FPGA of a Hopfield Neural Network

2011 ◽  
Vol 2011 ◽  
pp. 1-9 ◽  
Author(s):  
W. Mansour ◽  
R. Ayoubi ◽  
H. Ziade ◽  
R. Velazco ◽  
W. EL Falou
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
High Performance ◽  
Optimization Problems ◽  
Parallel Architecture ◽  
Hopfield Neural Network ◽  
Noise Removal ◽  
Combinatorial Optimization Problems ◽  
Artificial Neural Network Ann ◽  
Optimal Implementation

The associative Hopfield memory is a form of recurrent Artificial Neural Network (ANN) that can be used in applications such as pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper presents the implementation of the Hopfield Neural Network (HNN) parallel architecture on a SRAM-based FPGA. The main advantage of the proposed implementation is its high performance and cost effectiveness: it requires O(1) multiplications and O(log⁡ N) additions, whereas most others require O(N) multiplications and O(N) additions.

ASIC and board design of a high performance parallel architecture

2003 ◽  
Author(s):  
A. De Gloria ◽  
P. Faraboschi ◽  
M. Olivieri ◽  
E. Guidetti
Keyword(s):  
High Performance ◽  
Parallel Architecture

A Web-Lab Environment for the Study of the Job Shop Problem

2012 ◽  
Vol 463-464 ◽  
pp. 1073-1076
Author(s):  
Helmar Alvares ◽  
Eliana Prado Lopes Aude ◽  
Ernesto Prado Lopes
Keyword(s):  
High Performance ◽  
Job Shop ◽  
Response Times ◽  
Graphics Processing Unit ◽  
Low Cost ◽  
Parallel Architecture ◽  
Efficient Solutions ◽  
Processing Unit ◽  
Scheduling Problems ◽  
Solution Methods

This work proposes a Web-Based laboratory where researchers share the facilities of a simulation environment for parallel algorithms which solves scheduling problems known as Job Shop Problem (JSP). The environment supports multi-language platforms and uses a low cost, high performance Graphics Processing Unit (GPU) connected to a Java application server to help design more efficient solutions for JSP. Within a single web environment one can analyze and compare different methods and meta-heuristics. Each newly developed method is stored in an environment library and made available to all other users of the environment. This amassment of openly accessible solution methods will allow for the rapid convergence towards optimal solutions for JSP. The algorithm uses the parallel architecture of the system to handle threads. Each thread represents a job operation and the number of threads scales with the problem’s size. The threads exchange information in order to find the best solution. This cooperation decreases response times by one or two orders of magnitude.

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