Mapping method of coarse-grained dynamically reconfigurable computing system-on-chip of REMUS-II

2013 ◽  
Author(s):  
Xuexiang Wang ◽  
Hung K. Nguyen ◽  
Peng Cao ◽  
Zhi Qi ◽  
Hao Liu
Keyword(s):  
Reconfigurable Computing ◽  
Computing System ◽  
Mapping Method ◽  
System On Chip ◽  
Coarse Grained ◽  
Dynamically Reconfigurable ◽  
On Chip

scholarly journals Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip

2013 ◽  
Vol E96.D (3) ◽  
pp. 601-615 ◽  
Author(s):  
Hung K. NGUYEN ◽  
Peng CAO ◽  
Xue-Xiang WANG ◽  
Jun YANG ◽  
Longxing SHI ◽  
...  
Keyword(s):  
Reconfigurable Computing ◽  
Computing System ◽  
System On Chip ◽  
Coarse Grained ◽  
Dynamically Reconfigurable ◽  
On Chip

scholarly journals UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

2021 ◽  
Author(s):  
Dennis Wolf ◽  
Andreas Engel ◽  
Tajas Ruschke ◽  
Andreas Koch ◽  
Christian Hochberger
Keyword(s):  
Computing System ◽  
Coarse Grained ◽  
Instruction Level Parallelism ◽  
Control Engineering ◽  
Processing Elements ◽  
Actual Application ◽  
Reconfigurable Arrays ◽  
Engineering Environment ◽  
On Chip ◽  
Level Parallelism

AbstractCoarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements. These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.

scholarly journals Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

2018 ◽  
Vol 67 (12) ◽  
pp. 1818-1834 ◽  
Author(s):  
Weichen Liu ◽  
Lei Yang ◽  
Weiwen Jiang ◽  
Liang Feng ◽  
Nan Guan ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
Task Mapping ◽  
Dynamically Reconfigurable ◽  
On Chip
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