DReNoC: A dynamically reconfigurable computing system based on network-on-chip

2009 ◽  
Author(s):  
Ying-Chun Chen ◽  
Gao-Ming Du ◽  
Luo-Feng Geng ◽  
Duo-Li Zhang ◽  
Ming-Lun Gao
Keyword(s):  
Reconfigurable Computing ◽  
Computing System ◽  
Network On Chip ◽  
Dynamically Reconfigurable ◽  
On Chip

scholarly journals Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

2018 ◽  
Vol 67 (12) ◽  
pp. 1818-1834 ◽  
Author(s):  
Weichen Liu ◽  
Lei Yang ◽  
Weiwen Jiang ◽  
Liang Feng ◽  
Nan Guan ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
Task Mapping ◽  
Dynamically Reconfigurable ◽  
On Chip

scholarly journals Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System

2019 ◽  
Vol 15 (2) ◽  
pp. 115-128 ◽  
Author(s):  
Chidhambaranathan Rajamanikkam ◽  
J. S. Rajesh ◽  
Koushik Chakraborty ◽  
Sanghamitra Roy
Keyword(s):  
Energy Efficient ◽  
Computing System ◽  
Network On Chip ◽  
On Chip ◽  
Many Core ◽  
Near Threshold

scholarly journals A New Efficient and Reliable Dynamically ReconfigurableNetwork-on-Chip

2012 ◽  
Vol 2012 ◽  
pp. 1-16 ◽  
Author(s):  
Cédric Killian ◽  
Camel Tanougast ◽  
Fabrice Monteiro ◽  
Abbas Dandache
Keyword(s):  
Error Detection ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Data Packet ◽  
Reliable Operation ◽  
Detection Mechanism ◽  
Dynamically Reconfigurable ◽  
On Chip ◽  
Online Error Detection

We present a new reliableNetwork-on-Chip(NoC) suitable forDynamically Reconfigurable Multiprocessors on Chipsystems. The proposedNoCis based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of theNoC. The main originality in the proposedNoCis that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in theNoCwithout data packet loss thanks to a self-loopbackmechanism inside each router.

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