RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip

2009 ◽  
Author(s):  
F. Campi ◽  
R. Konig ◽  
M. Dreschmann ◽  
M. Neukirchner ◽  
D. Picard ◽  
...  
Keyword(s):  
Reconfigurable Computing ◽  
Coarse Grained ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
On Chip

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

2010 ◽  
pp. 28-66 ◽  
Author(s):  
Mário P. Véstias ◽  
Horácio C. Neto
Keyword(s):  
Quality Of Service ◽  
Power Consumption ◽  
First Generation ◽  
Networks On Chip ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
High Bandwidth ◽  
Area Occupation ◽  
On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip

2018 ◽  
Vol 112 ◽  
pp. 1-19 ◽  
Author(s):  
Gilberto Ochoa-Ruiz ◽  
Pamela Wattebled ◽  
Maamar Touiza ◽  
Florent De Lamotte ◽  
El-Bay Bourennane ◽  
...  
Keyword(s):  
Reconfigurable Systems ◽  
Context Aware ◽  
Dynamically Reconfigurable ◽  
Front End ◽  
Systems On Chip ◽  
On Chip ◽  
Seamless Design

scholarly journals Implementation of Dynamically Reconfigurable Systems on Chip with OS Support

2012 ◽  
Vol 49 (6) ◽  
pp. 33-35
Author(s):  
Vaibhawa Mishra ◽  
Kota Solomon Raju ◽  
Pramod Kumar Tanwar
Keyword(s):  
Reconfigurable Systems ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
On Chip

Adaptive multi-layer techniques for increased system dependability

2015 ◽  
Vol 57 (3) ◽  
Author(s):  
Lars Bauer ◽  
Jörg Henkel ◽  
Andreas Herkersdorf ◽  
Michael A. Kochte ◽  
Johannes M. Kühn ◽  
...  
Keyword(s):  
General Purpose ◽  
System Level ◽  
Coarse Grained ◽  
Common Goal ◽  
Fine Grained ◽  
Reconfigurable Processors ◽  
Systems On Chip ◽  
On Chip ◽  
Application Specific ◽  
Heterogeneous Mpsoc

AbstractAchieving system-level dependability is a demanding task. The manifold requirements and dependability threats can no longer be statically addressed at individual abstraction layers. Instead, all components of future multi-processor systems-on-chip (MPSoCs) have to contribute to this common goal in an adaptive manner.In this paper we target a generic heterogeneous MPSoC that combines general purpose processors along with dedicated application-specific hard-wired accelerators, fine-grained reconfigurable processors, and coarse-grained reconfigurable architectures. We present different

scholarly journals The approach to design of dynamically reconfigurable arbitration units in embedded systems

2019 ◽  
Vol 29 (3) ◽  
pp. 55-67
Author(s):  
E. A. Suvorova
Keyword(s):  
Embedded Systems ◽  
Complex Function ◽  
Reconfigurable Systems ◽  
Design Rules ◽  
Networks On Chip ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
Function Modules ◽  
On Chip ◽  
Intensive Development

Today we are seeing an intensive development of dynamically reconfigurable components in the FPGA-based embedded systems. Nevertheless, by their parameters, FPGA-based projects are essentially inferior to those that are on ASIC and the same design rules. This significantly limits applications of the FPGA-based reconfigurable systems. The paper presents relevance of dynamic reconfiguration for arbitration units in embedded systems. There is a review of existing design techniques for ASIC-based dynamically reconfigurable components. They have been also evaluated by applicability for the arbitration unit development (complex function modules for systems-on-chip and networks-on-chip). The authors have proposed the approach to the development of dynamically reconfigurable arbitration units in embedded systems. The approach makes it possible to consider specific requirements to these units.

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