SiGe SEG Growth for Buried Channels p-MOS Devices

2019 ◽  
Vol 25 (7) ◽  
pp. 201-210 ◽  
Author(s):  
Andriy Hikavyy ◽  
Roger Loo ◽  
Liesbeth Witters ◽  
Shinji Takeoka ◽  
Jef Geypen ◽  
...  
Keyword(s):  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.


2007 ◽  
Vol 28 (5) ◽  
pp. 432-435 ◽  
Author(s):  
Chun-Yuan Lu ◽  
Kuei-Shu Chang-Liao ◽  
Chun-Chang Lu ◽  
Ping-Hung Tsai ◽  
Tien-Ko Wang

2010 ◽  
Vol 1 (2) ◽  
pp. 105-109
Author(s):  
V. V. Andreev ◽  
G. G. Bondarenko ◽  
A. A. Stolyarov ◽  
D. S. Vasyutin ◽  
A. M. Mikhal’kov

1991 ◽  
Vol 22 (1) ◽  
pp. 23-29 ◽  
Author(s):  
D. Simeonov ◽  
E. Goranova
Keyword(s):  

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