1.3 kV Vertical GaN-Based Trench MOSFETs on 4-Inch Free Standing GaN Wafer

In this work, a vertical gallium nitride (GaN)-based trench MOSFET on 4-inch free-standing GaN substrate is presented with threshold voltage of 3.15 V, specific on-resistance of 1.93 mΩ·cm2, breakdown voltage of 1306 V, and figure of merit of 0.88 GW/cm2. High-quality and stable MOS interface is obtained through two-step process, including simple acid cleaning and a following (NH4)2S passivation. Based on the calibration with experiment, the simulation results of physical model are consistent well with the experiment data in transfer, output, and breakdown characteristic curves, which demonstrate the validity of the simulation data obtained by Silvaco technology computer aided design (Silvaco TCAD). The mechanisms of on-state and breakdown are thoroughly studied using Silvaco TCAD physical model. The device parameters, including n−-GaN drift layer, p-GaN channel layer and gate dielectric layer, are systematically designed for optimization. This comprehensive analysis and optimization on the vertical GaN-based trench MOSFETs provide significant guide for vertical GaN-based high power applications.

Top-gate field-effect transistor based on monolayer WS2 with an ion-gel gate dielectric

A top-gate field-effect transistor (FET), based on monolayer (ML) tungsten disulfide (WS2), and with an ion-gel dielectric was developed. The high electrical contact resistance of the Schottky contacts at the n-type transition metal dichalcogenides/metal electrode interfaces often adversely affects the device performance. We report the contact resistance and Schottky barrier height of an FET with Au electrodes. The FET is based on ML WS2 that was synthesised using chemical vapour deposition and was assessed using the transfer-length method and low-temperature measurements. Raman and photoluminescence spectra were recorded to determine the optical properties of the WS2 layers. The ML WS2 FET with an ion-gel top gate dielectric exhibits n-type behaviour, with a mobility, on/off ratio of 1.97 cm2/V·s, 1.51×105, respectively.

Phase Properties of Different HfO2 Polymorphs: A DFT-Based Study

Background: Hafnium Dioxide (HfO2) represents a hopeful material for gate dielectric thin films in the field of semiconductor integrated circuits. For HfO2, several crystal structures are possible, with different properties which can be difficult to describe in detail from an experimental point of view. In this study, a detailed computational approach has been shown to present a complete analysis of four HfO2 polymorphs, outlining the intrinsic properties of each phase on the basis of atomistic displacements. Methods: Density functional theory (DFT) based methods have been used to accurately describe the chemical physical properties of the polymorphs. Corrective Hubbard (U) semi-empirical terms have been added to exchange correlation energy in order to better reproduce the excited-state properties of HfO2 polymorphs. Results: the monoclinic phase resulted in the lowest cohesive energy, while the orthorhombic showed peculiar properties due to its intrinsic ferroelectric behavior. DFT + U methods showed the different responses of the four polymorphs to an applied field, and the orthorhombic phase was the least likely to undergo point defects as oxygen vacancies. Conclusions: The obtained results give a deeper insight into the differences in excited states phenomena in relation to each specific HfO2 polymorph.

Study of the impact of interface traps associated with SiNX passivation on AlGaN/GaN MIS-HEMTs

In this work, we show that a bilayer SiNx passivation scheme which includes a high-temperature annealed SiNx as gate dielectric, significantly improves both ON and OFF state performance of AlGaN/GaN MISHEMTs. From devices with different SiNx passivation schemes, surface and bulk leakage paths were determined. Temperature-dependent MESA leakage studies showed that the surface conduction could be explained using a 2-D variable range hopping mechanism along with the mid-gap interface states at the GaN(cap)/ SiNx interface generated due to the Ga-Ga metal like bonding states. It was found that the high temperature annealed SiNx gate dielectric exhibited the lowest interface state density and a two-step C-V indicative of a superior quality SiNx/GaN interface as confirmed from conductance and capacitance measurements. High-temperature annealing helps in the formation of Ga-N bonding states, thus reducing the shallow metal-like interface states. MISHEMT measurements showed a significant reduction in gate leakage and a 4-orders of magnitude improvement in the ON/OFF ratio while increasing the saturation drain current (IDS) by a factor of 2. Besides, MISHEMTs with 2-step SiNx passivation exhibited a relatively flat transconductance profile, indicative of lower interface states density. The dynamic Ron with gate and drain stressing measurements also showed about 3x improvements in devices with bilayer SiNx passivation.

МДП транзистор на основе пленки PbSnTe : In с подзатворным диэлектриком Al-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=--=SUP=-*-=/SUP=-

Results on the creation and properties of transistor-type MIS structures (MIST) with an Al2O3 thin-film gate dielectric based on PbSnTe:In films obtained by molecular beam epitaxy are presented. The source-drain current-voltage characteristics (CVC) and gate characteristics of the MIST at Т = 4.2 К have been investigated. It is shown that in MIST based on PbSnTe:In films with n ~ 1017 cm-3 the modulation of the channel current reaches 7 – 8 % in the range of gate voltages – 10 V < Ugate < + 10 V. The features of the source-drain CVC and the gate characteristics for a pulsed and sawtooth variation of Ugate are considered.

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.