scholarly journals A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

2017 ◽  
Vol 2017 ◽  
pp. 1-12
Author(s):  
Andreas G. Savva ◽  
Theocharis Theocharides ◽  
Chrysostomos Nicopoulos
Keyword(s):  
Fault Detection ◽  
Design Space Exploration ◽  
Design Space ◽  
Generalization Capability ◽  
Networks On Chip ◽  
Traffic Models ◽  
Artificial Neural Network Ann ◽  
On Chip ◽  
High Level

This work presents a design exploration framework for developing a high level Artificial Neural Network (ANN) for fault detection in hardware systems. ANNs can be used for fault detection purposes since they have excellent characteristics such as generalization capability, robustness, and fault tolerance. Designing an ANN in order to be used for fault detection purposes includes different parameters. Through this work, those parameters are presented and analyzed based on simulations. Moreover, after the development of the ANN, in order to evaluate it, a case study scenario based on Networks on Chip is used for detection of interrouter link faults. Simulation results with various synthetic traffic models show that the proposed work can detect up to 96–99% of interrouter link faults with a delay less than 60 cycles. Added to this, the size of the ANN is kept relatively small and they can be implemented in hardware easily. Synthesis results indicate an estimated amount of 0.0523 mW power consumption per neuron for the implemented ANN when computing a complete cycle.

scholarly journals A Signature-Based Power Model for MPSoC on FPGA

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-13 ◽  
Author(s):  
Roberta Piscitelli ◽  
Andy D. Pimentel
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Power Estimation ◽  
System Level ◽  
Estimation Methods ◽  
Instruction Set ◽  
Systems On Chip ◽  
Event Signatures ◽  
On Chip ◽  
High Level

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

A networks-on-chip architecture design space exploration – The LIB

2009 ◽  
Vol 35 (6) ◽  
pp. 817-836 ◽  
Author(s):  
Peng Liu ◽  
Bingjie Xia ◽  
Chunchang Xiang ◽  
Xiaohang Wang ◽  
Weidong Wang ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Architecture Design ◽  
Networks On Chip ◽  
On Chip

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

2010 ◽  
Vol 1 (1) ◽  
pp. 86-101 ◽  
Author(s):  
Sanna Määttä ◽  
Leandro Möller ◽  
Leandro Soares Indrusiak ◽  
Luciano Ost ◽  
Manfred Glesner ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Network On Chip ◽  
Multiprocessor Systems ◽  
Single Application ◽  
Successive Refinement ◽  
Systems On Chip ◽  
On Chip ◽  
Abstraction Levels

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

Sign in / Sign up

Export Citation Format

Share Document