scholarly journals A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations

2021 ◽  
Vol 2021 ◽  
pp. 1-29
Author(s):  
Dimple Sharma ◽  
Lev Kirischian
Keyword(s):  
Decision Making ◽  
Embedded Systems ◽  
Mobile Systems ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
External Temperature ◽  
Power Sources ◽  
Die Temperature ◽  
Run Time

One of the growing areas of application of embedded systems in robotics, aerospace, military, etc. is autonomous mobile systems. Usually, such embedded systems have multitask multimodal workloads. These systems must sustain the required performance of their dynamic workloads in presence of varying power budget due to rechargeable power sources, varying die temperature due to varying workloads and/or external temperature, and varying hardware resources due to occurrence of hardware faults. This paper proposes a run-time decision-making method, called Decision Space Explorer, for FPGA-based Systems-on-Chip (SoCs) to support changing workload requirements while simultaneously mitigating unpredictable variations in power budget, die temperature, and hardware resource constraints. It is based on the concept of Run-Time Structural Adaptation (RTSA); whenever there is a change in a system’s set of constraints, Explorer selects a suitable hardware processing circuit for each active task at an appropriate operating frequency such that all the constraints are satisfied. Explorer has been experimentally deployed on the ARM Cortex-A9 core of Xilinx Zynq XC7Z020 SoC. Its worst-case decision-making time for different scenarios ranges from tens to hundreds of microseconds. Explorer is thus suitable for enabling RTSA in systems where specifications of multiple objectives must be maintained simultaneously, making them self-sustainable.

scholarly journals A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

2021 ◽  
Vol 2021 ◽  
pp. 1-20
Author(s):  
Dimple Sharma ◽  
Lev Kirischian
Keyword(s):  
Decision Making ◽  
Power Consumption ◽  
Thermal Cycling ◽  
Mobile Systems ◽  
Structural Adaptation ◽  
Estimation Model ◽  
Power Budget ◽  
Potential System ◽  
Die Temperature ◽  
Run Time

Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads. For such field-deployed systems, activation times, execution periods of tasks, and variations in environmental conditions are usually difficult to predict. These dynamic variations result in a new challenge of dynamic thermal cycling stress on the SoPC die, which can result in transient and even permanent hardware faults in the computing system. This paper proposes the approach of run-time structural adaptation (RTSA) to mitigate dynamic thermal cycling stress on the SoPC dies. RTSA assumes the tasks to have multiple implementation variants, called Application Specific Processing (ASP) circuit variants, which vary in hardware resources, operating frequency, and power consumption. Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of operation. This means the essence of RTSA is a decision-making mechanism which can select at run-time, a suitable system configuration (set of ASP circuit variants of active tasks), whenever needed, to meet the die temperature constraints. To do so, run-time die temperature prediction for potential system configurations using an estimation model is required. This paper presents a generic method to derive an analytical model for any SoPC that can estimate the die temperature in real time and thus support the decision-making mechanism. To develop this method, the thermal behavior of SoPC die under different task scenarios is studied and relation of die temperature to frequency, resource utilization, and power consumption is analyzed. An RTSA-enabled experimental platform is set up on Xilinx Zynq XC7Z020 SoPC for this purpose. Experimental results also demonstrate that the proposed method can be used to derive a model in run-time, thus enabling systems to self-derive and dynamically update the model in run-time.

scholarly journals Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

2021 ◽  
Author(s):  
Dimple Sharma ◽  
Lev Kirischian ◽  
Valeri Kirischian
Keyword(s):  
Autonomous Vehicles ◽  
Resource Constraints ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
Power Sources ◽  
Hardware Resource ◽  
Run Time ◽  
System On Programmable Chip ◽  
Hardware Faults

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

scholarly journals Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Computers ◽  
2018 ◽  
Vol 7 (4) ◽  
pp. 52 ◽  
Author(s):  
Dimple Sharma ◽  
Lev Kirischian ◽  
Valeri Kirischian
Keyword(s):  
Autonomous Vehicles ◽  
Resource Constraints ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
Power Sources ◽  
Hardware Resource ◽  
Run Time ◽  
System On Programmable Chip ◽  
Hardware Faults

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

scholarly journals Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

2021 ◽  
Author(s):  
Dimple Sharma ◽  
Lev Kirischian ◽  
Valeri Kirischian
Keyword(s):  
Autonomous Vehicles ◽  
Resource Constraints ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
Power Sources ◽  
Hardware Resource ◽  
Run Time ◽  
System On Programmable Chip ◽  
Hardware Faults

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

Efficiently Handling Process Overruns and Underruns on Multiprocessors in Real-Time Embedded Systems

2017 ◽  
Author(s):  
Jia Xu
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Time Complexity ◽  
Multiprocessor System ◽  
Multiprocessor Systems ◽  
Worst Case ◽  
Real World Applications ◽  
Run Time ◽  
Hard Real Time ◽  
Time Overhead

In hard real-time and embedded multiprocessor system real-world applications, it is very important to strive to minimize the run-time overhead of the scheduler as much as possible, especially in hard real-time and embedded multiprocessor systems with limited processor and system resources. In this paper, we present a method that reduces the worst-case time complexity of the run-time scheduler for re-computing latest start times and for selecting processes for execution on a multiprocessor at run-time to O(n), where n is the number of processes.

Efficiently Handling Process Overruns and Underruns in Real-Time Embedded Systems

2015 ◽  
Author(s):  
Jia Xu
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Time Process ◽  
Time System ◽  
Worst Case ◽  
Real Time System ◽  
System Utilization ◽  
System Overhead ◽  
Run Time

Methods for handling process underruns and overruns when scheduling a set of real-time processes increase both system utilization and robustness in the presence of inaccurate estimates of the worst-case computations of real-time processes. In this paper, we present a method that efficiently re-computes latest start times for real time processes during run-time in the event that a real-time process is preempted or has completed (or overrun). The method effectively identifies which process latest start times will be affected by the preemption or completion of a process. Hence the method is able to effectively reduce real-time system overhead by selectively re-computing latest start times for the specific processes whose latest start times are changed by a process preemption or completion, as opposed to indiscriminately re-computing latest start times for all the processes.

Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽  
2009 ◽  
Author(s):  
Moshe Pelleh
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
General Purpose ◽  
Experimental Results ◽  
Medium Size ◽  
Organic System ◽  
Software Application ◽  
Organic Systems ◽  
Special Cases ◽  
Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

scholarly journals Improving the Smoothed Complexity of FLIP for Max Cut Problems

2021 ◽  
Vol 17 (3) ◽  
pp. 1-38
Author(s):  
Ali Bibak ◽  
Charles Carlson ◽  
Karthekeyan Chandrasekaran
Keyword(s):  
General Framework ◽  
Edge Weight ◽  
Complete Graphs ◽  
Worst Case ◽  
Weight Density ◽  
Complete Problems ◽  
Substantial Progress ◽  
Run Time ◽  
Optimum Solution ◽  
Arbitrary Graphs

Finding locally optimal solutions for MAX-CUT and MAX- k -CUT are well-known PLS-complete problems. An instinctive approach to finding such a locally optimum solution is the FLIP method. Even though FLIP requires exponential time in worst-case instances, it tends to terminate quickly in practical instances. To explain this discrepancy, the run-time of FLIP has been studied in the smoothed complexity framework. Etscheid and Röglin (ACM Transactions on Algorithms, 2017) showed that the smoothed complexity of FLIP for max-cut in arbitrary graphs is quasi-polynomial. Angel, Bubeck, Peres, and Wei (STOC, 2017) showed that the smoothed complexity of FLIP for max-cut in complete graphs is ( O Φ 5 n 15.1 ), where Φ is an upper bound on the random edge-weight density and Φ is the number of vertices in the input graph. While Angel, Bubeck, Peres, and Wei’s result showed the first polynomial smoothed complexity, they also conjectured that their run-time bound is far from optimal. In this work, we make substantial progress toward improving the run-time bound. We prove that the smoothed complexity of FLIP for max-cut in complete graphs is O (Φ n 7.83 ). Our results are based on a carefully chosen matrix whose rank captures the run-time of the method along with improved rank bounds for this matrix and an improved union bound based on this matrix. In addition, our techniques provide a general framework for analyzing FLIP in the smoothed framework. We illustrate this general framework by showing that the smoothed complexity of FLIP for MAX-3-CUT in complete graphs is polynomial and for MAX - k - CUT in arbitrary graphs is quasi-polynomial. We believe that our techniques should also be of interest toward showing smoothed polynomial complexity of FLIP for MAX - k - CUT in complete graphs for larger constants k .

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