scholarly journals A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

2021 ◽  
Vol 2021 ◽  
pp. 1-20
Author(s):  
Dimple Sharma ◽  
Lev Kirischian
Keyword(s):  
Decision Making ◽  
Power Consumption ◽  
Thermal Cycling ◽  
Mobile Systems ◽  
Structural Adaptation ◽  
Estimation Model ◽  
Power Budget ◽  
Potential System ◽  
Die Temperature ◽  
Run Time

Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads. For such field-deployed systems, activation times, execution periods of tasks, and variations in environmental conditions are usually difficult to predict. These dynamic variations result in a new challenge of dynamic thermal cycling stress on the SoPC die, which can result in transient and even permanent hardware faults in the computing system. This paper proposes the approach of run-time structural adaptation (RTSA) to mitigate dynamic thermal cycling stress on the SoPC dies. RTSA assumes the tasks to have multiple implementation variants, called Application Specific Processing (ASP) circuit variants, which vary in hardware resources, operating frequency, and power consumption. Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of operation. This means the essence of RTSA is a decision-making mechanism which can select at run-time, a suitable system configuration (set of ASP circuit variants of active tasks), whenever needed, to meet the die temperature constraints. To do so, run-time die temperature prediction for potential system configurations using an estimation model is required. This paper presents a generic method to derive an analytical model for any SoPC that can estimate the die temperature in real time and thus support the decision-making mechanism. To develop this method, the thermal behavior of SoPC die under different task scenarios is studied and relation of die temperature to frequency, resource utilization, and power consumption is analyzed. An RTSA-enabled experimental platform is set up on Xilinx Zynq XC7Z020 SoPC for this purpose. Experimental results also demonstrate that the proposed method can be used to derive a model in run-time, thus enabling systems to self-derive and dynamically update the model in run-time.

scholarly journals A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations

2021 ◽  
Vol 2021 ◽  
pp. 1-29
Author(s):  
Dimple Sharma ◽  
Lev Kirischian
Keyword(s):  
Decision Making ◽  
Embedded Systems ◽  
Mobile Systems ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
External Temperature ◽  
Power Sources ◽  
Die Temperature ◽  
Run Time

One of the growing areas of application of embedded systems in robotics, aerospace, military, etc. is autonomous mobile systems. Usually, such embedded systems have multitask multimodal workloads. These systems must sustain the required performance of their dynamic workloads in presence of varying power budget due to rechargeable power sources, varying die temperature due to varying workloads and/or external temperature, and varying hardware resources due to occurrence of hardware faults. This paper proposes a run-time decision-making method, called Decision Space Explorer, for FPGA-based Systems-on-Chip (SoCs) to support changing workload requirements while simultaneously mitigating unpredictable variations in power budget, die temperature, and hardware resource constraints. It is based on the concept of Run-Time Structural Adaptation (RTSA); whenever there is a change in a system’s set of constraints, Explorer selects a suitable hardware processing circuit for each active task at an appropriate operating frequency such that all the constraints are satisfied. Explorer has been experimentally deployed on the ARM Cortex-A9 core of Xilinx Zynq XC7Z020 SoC. Its worst-case decision-making time for different scenarios ranges from tens to hundreds of microseconds. Explorer is thus suitable for enabling RTSA in systems where specifications of multiple objectives must be maintained simultaneously, making them self-sustainable.

scholarly journals Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

2021 ◽  
Author(s):  
Dimple Sharma ◽  
Lev Kirischian ◽  
Valeri Kirischian
Keyword(s):  
Autonomous Vehicles ◽  
Resource Constraints ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
Power Sources ◽  
Hardware Resource ◽  
Run Time ◽  
System On Programmable Chip ◽  
Hardware Faults

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

scholarly journals Energy-Efficient Hybrid Unicore Architecture In Future Embedded Chip-Multiprocessor

2021 ◽  
Author(s):  
Akram Hadeed
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Energy Efficient ◽  
Access Time ◽  
Hybrid Architecture ◽  
Operational Parameters ◽  
Power Budget ◽  
Voltage Frequency ◽  
Run Time ◽  
On Chip

Recently, technology scaling has enabled the placement of an increasing number of cores, in the form of chip-multiprocessors (CMPs) on a chip and continually shrinking transistor sizes to improve performance. In this context, power consumption has become the main constraint in designing CMPs. As a result, uncore components power consumption taking increasing portion from the on-chip power budget; therefore, designing power management techniques, particularly memory and network-on-chip (NoC) systems, has become an important issue to solve. Consequently, a considerable attention has been directed toward power management based on CMPs components, particularly shared caches and uncore interconnected structures, to overcome the challenges of limited chip power budget.<div>This work targets to design an energy-efficient uncore architecture by using heterogeneity in components (cache cells) and operational parameters (Voltage/Frequency). In order to ensure the minimum impact on the system performance, a run-time approach is investigated to assess the proposed method. An architecture is proposed where the cache layer contains the heterogenous cache banks in all placed in one frequency voltage domain. Average memory access time (AMAT) was selected as a network monitor to monitor the performance on the run-time. The appropriate size and type of the last level cache (LLC) and Voltage/Frequency for the uncore domain is adjusted according to the calculated AMAT which indicates the system demand from the uncore.<br></div><div>The proposed hybrid architecture was implemented, investigated and compared with the a baseline model where only SRAM banks were used in the last level cache. Experimental results on the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suit,show that the proposed architecture yields up to a 40% reduction in overall chip energy-delay product with a marginal performance degradation in average of -1.2% below the baseline one. The best energy saving was 55% and the worse degradation was only 15%.<br></div>

Energy-Efficient Hybrid Unicore Architecture In Future Embedded Chip-Multiprocessor

2021 ◽  
Author(s):  
Akram Hadeed
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Energy Efficient ◽  
Access Time ◽  
Hybrid Architecture ◽  
Operational Parameters ◽  
Power Budget ◽  
Voltage Frequency ◽  
Run Time ◽  
On Chip

Recently, technology scaling has enabled the placement of an increasing number of cores, in the form of chip-multiprocessors (CMPs) on a chip and continually shrinking transistor sizes to improve performance. In this context, power consumption has become the main constraint in designing CMPs. As a result, uncore components power consumption taking increasing portion from the on-chip power budget; therefore, designing power management techniques, particularly memory and network-on-chip (NoC) systems, has become an important issue to solve. Consequently, a considerable attention has been directed toward power management based on CMPs components, particularly shared caches and uncore interconnected structures, to overcome the challenges of limited chip power budget.<div>This work targets to design an energy-efficient uncore architecture by using heterogeneity in components (cache cells) and operational parameters (Voltage/Frequency). In order to ensure the minimum impact on the system performance, a run-time approach is investigated to assess the proposed method. An architecture is proposed where the cache layer contains the heterogenous cache banks in all placed in one frequency voltage domain. Average memory access time (AMAT) was selected as a network monitor to monitor the performance on the run-time. The appropriate size and type of the last level cache (LLC) and Voltage/Frequency for the uncore domain is adjusted according to the calculated AMAT which indicates the system demand from the uncore.<br></div><div>The proposed hybrid architecture was implemented, investigated and compared with the a baseline model where only SRAM banks were used in the last level cache. Experimental results on the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suit,show that the proposed architecture yields up to a 40% reduction in overall chip energy-delay product with a marginal performance degradation in average of -1.2% below the baseline one. The best energy saving was 55% and the worse degradation was only 15%.<br></div>

scholarly journals Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Computers ◽  
2018 ◽  
Vol 7 (4) ◽  
pp. 52 ◽  
Author(s):  
Dimple Sharma ◽  
Lev Kirischian ◽  
Valeri Kirischian
Keyword(s):  
Autonomous Vehicles ◽  
Resource Constraints ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
Power Sources ◽  
Hardware Resource ◽  
Run Time ◽  
System On Programmable Chip ◽  
Hardware Faults

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

scholarly journals Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

2021 ◽  
Author(s):  
Dimple Sharma ◽  
Lev Kirischian ◽  
Valeri Kirischian
Keyword(s):  
Autonomous Vehicles ◽  
Resource Constraints ◽  
Structural Adaptation ◽  
Power Budget ◽  
Worst Case ◽  
Power Sources ◽  
Hardware Resource ◽  
Run Time ◽  
System On Programmable Chip ◽  
Hardware Faults

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

scholarly journals An Estimation of Ship Collision Risk Based on Relevance Vector Machine

2021 ◽  
Vol 9 (5) ◽  
pp. 538
Author(s):  
Jinwan Park ◽  
Jung-Sik Jeong
Keyword(s):  
Machine Learning ◽  
Decision Making ◽  
Risk Estimation ◽  
Good Method ◽  
Relevance Vector Machine ◽  
Machine Learning Algorithms ◽  
Support Vector ◽  
Collision Risk ◽  
Estimation Model ◽  
Ship Collision

According to the statistics of maritime collision accidents over the last five years (2016–2020), 95% of the total maritime collision accidents are caused by human factors. Machine learning algorithms are an emerging approach in judging the risk of collision among vessels and supporting reliable decision-making prior to any behaviors for collision avoidance. As the result, it can be a good method to reduce errors caused by navigators’ carelessness. This article aims to propose an enhanced machine learning method to estimate ship collision risk and to support more reliable decision-making for ship collision risk. In order to estimate the ship collision risk, the conventional support vector machine (SVM) was applied. Regardless of the advantage of the SVM to resolve the uncertainty problem by using the collected ships’ parameters, it has inherent weak points. In this study, the relevance vector machine (RVM), which can present reliable probabilistic results based on Bayesian theory, was applied to estimate the collision risk. The proposed method was compared with the results of applying the SVM. It showed that the estimation model using RVM is more accurate and efficient than the model using SVM. We expect to support the reasonable decision-making of the navigator through more accurate risk estimation, thus allowing early evasive actions.

scholarly journals Highly Reliable Decision-Making Using Reliability Factor Feedback for Factory Condition Monitoring via WSNs

2018 ◽  
Vol 2018 ◽  
pp. 1-9 ◽  
Author(s):  
Zafar Iqbal ◽  
Heung-No Lee ◽  
Saeid Nooshabadi
Keyword(s):  
Decision Making ◽  
Power Consumption ◽  
Cluster Head ◽  
Base Station ◽  
False Alarms ◽  
Delivery Ratio ◽  
Probability Of Error ◽  
Reliability Factor ◽  
Packet Delivery ◽  
Low Level

Cooperation among sensors in a wireless sensor network, deployed for industrial monitoring in an indoor scenario, is a topic of interest in the smart factory and smart city research. The indoor wireless communication channel is very harsh and the observations of all the sensors cannot be sent reliably to the base station. Failure to transmit correct sensing results to the base station may result in false alarms or missed detection of events. Therefore, we propose a cooperation scheme for the wireless sensors to send the data reliably to the base station. Our aim is to increase the reliability of the received information, reduce the probability of error, lower the overall power consumption, and keep the latency to an acceptable low level. We propose a reliability factor feedback algorithm to adjust the weight of unreliable sensors in the decision-making process. The proposed scheme is analyzed based on its latency, power consumption, and packet delivery ratio. Our results show significant improvement in the reliability of the received data, improved packet delivery, and reduced false alarm ratio for full repetition and cluster head-based cooperation. The power consumption and latency in data transmission are also kept to an acceptable low level.

Temperature-Power Consumption Relationship and Hot-Spot Migration for FPGA-Based Systems

2013 ◽  
pp. 377-396
Author(s):  
Xun Zhang ◽  
Pierre Leray ◽  
Jacques Palicot
Keyword(s):  
Decision Making ◽  
Cognitive Radio ◽  
Power Consumption ◽  
Electronic Device ◽  
Hot Spot ◽  
Local Heat ◽  
Heat Emission ◽  
Thermal Sensor ◽  
Dynamically Reconfigurable ◽  
Highly Correlated

Heat emission and temperature control in an electronic device are highly correlated with power consumption as well as to equipment’s reliability. Within this context, this chapter discusses a possible solution to restrict the processing component’s heat emission in FPGA-based systems (e.g., Cognitive Radio [CR] equipment). It also describes the implementation, on reconfigurable FPGA based circuit, of a digital thermal sensor, analyzes the applicability of local heat estimations, and empirically describes the temperature-power consumption relationship in a dynamically reconfigurable FPGA platform. Finally, discussions are conducted on the decision making issues related to the use of such sensors to enable “hot-spot” migration in CR equipment.

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