Synthesis at the Register Transfer Level and the Behavioral Level

Design Automation, Languages, and Simulations ◽

10.1201/9780203009284.ch3 ◽

2003 ◽

pp. 3-1-3-26

Author(s):

J Bhasker

Keyword(s):

Register Transfer Level ◽

Behavioral Level ◽

Register Transfer

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Synthesis at the Register Transfer Level and the Behavioral Level

Knowledge Management ◽

10.1201/9781420041125.ch65 ◽

2001 ◽

Author(s):

J Bhasker

Keyword(s):

Register Transfer Level ◽

Behavioral Level ◽

Register Transfer

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Synthesis at the Register Transfer Level and the Behavioral Level

The VLSI Handbook ◽

10.1201/9781420049671-79 ◽

1999 ◽

pp. 1596-1622

Keyword(s):

Register Transfer Level ◽

Behavioral Level ◽

Register Transfer

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Synthesis at the Register Transfer Level and the Behavioral Level Jay Bhasker

The Circuits and Filters Handbook ◽

10.1201/9781420041408-68 ◽

2002 ◽

pp. 2121-2146

Keyword(s):

Register Transfer Level ◽

Behavioral Level ◽

Register Transfer

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Synthesis at the Register Transfer Level and the Behavioral Level

Electrical Engineering Handbook - The VLSI Handbook ◽

10.1201/9781420049671.ch75 ◽

1999 ◽

Author(s):

J Bhasker

Keyword(s):

Register Transfer Level ◽

Behavioral Level ◽

Register Transfer

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Synthesis at the Register Transfer Level and the Behavioral Level

Design Automation, Languages, and Simulations ◽

10.1201/9780203009284-5 ◽

2003 ◽

pp. 65-90

Keyword(s):

Register Transfer Level ◽

Behavioral Level ◽

Register Transfer

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Standard for Verilog register transfer level synthesis

10.3403/30128339u ◽

2015 ◽

Keyword(s):

Register Transfer Level ◽

Register Transfer

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Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2406 ◽

2011 ◽

Vol 2 (4) ◽

pp. 61-68

Author(s):

M S Suma

Keyword(s):

Fault Modeling ◽

Register Transfer Level ◽

Sequential Circuits ◽

Register Transfer ◽

Combinational And Sequential Circuits

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Incorporating the controller effects during register transfer level synthesis

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326916 ◽

2002 ◽

Author(s):

C. Ramachandran ◽

F.J. Kurdahi

Keyword(s):

Register Transfer Level ◽

Register Transfer

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A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368825 ◽

2000 ◽

Author(s):

Satoshi Ohtake ◽

Hiroki Wada ◽

Toshimitsu Masuzawa ◽

Hideo Fujiwara

Keyword(s):

Register Transfer Level ◽

Register Transfer

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Test pattern generators for distributed and embedded built-in self-test at register transfer level

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915236 ◽

2002 ◽

Author(s):

V. Vorisek

Keyword(s):

Test Pattern ◽

Register Transfer Level ◽

Register Transfer ◽

Self Test ◽

Built In Self Test ◽

Pattern Generators

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