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A non-scan DFT method at register-transfer level to achieve complete fault efficiency
Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00
◽
10.1145/368434.368825
◽
2000
◽
Cited By ~ 12
Author(s):
Satoshi Ohtake
◽
Hiroki Wada
◽
Toshimitsu Masuzawa
◽
Hideo Fujiwara
Keyword(s):
Dft Method
◽
Register Transfer Level
◽
Register Transfer
Download Full-text
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Cited By
References
A DFT Method for Time Expansion Model at Register Transfer Level
2007 44th ACM/IEEE Design Automation Conference
◽
10.1109/dac.2007.375251
◽
2007
◽
Cited By ~ 1
Author(s):
Hiroyuki Iwata
◽
Tomokazu Yoneda
◽
Hideo Fujiwara
Keyword(s):
Dft Method
◽
Register Transfer Level
◽
Register Transfer
◽
Time Expansion
◽
Expansion Model
Download Full-text
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)
◽
10.1109/aspdac.2000.835171
◽
2002
◽
Cited By ~ 5
Author(s):
S. Ohtake
◽
H. Wada
◽
T. Masuzawa
◽
H. Fujiwara
Keyword(s):
Dft Method
◽
Register Transfer Level
◽
Register Transfer
Download Full-text
A DFT method for time expansion model at register transfer level
2007 44th ACM/IEEE Design Automation Conference
◽
10.1145/1278480.1278652
◽
2007
◽
Cited By ~ 1
Author(s):
Hiroyuki Iwata
◽
Tomokazu Yoneda
◽
Hideo Fujiwara
Keyword(s):
Dft Method
◽
Register Transfer Level
◽
Register Transfer
◽
Time Expansion
◽
Expansion Model
Download Full-text
Standard for Verilog register transfer level synthesis
10.3403/30128339u
◽
2015
◽
Keyword(s):
Register Transfer Level
◽
Register Transfer
Download Full-text
Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level
International Journal of VLSI Design & Communication Systems
◽
10.5121/vlsic.2011.2406
◽
2011
◽
Vol 2
(4)
◽
pp. 61-68
Author(s):
M S Suma
Keyword(s):
Fault Modeling
◽
Register Transfer Level
◽
Sequential Circuits
◽
Register Transfer
◽
Combinational And Sequential Circuits
Download Full-text
Incorporating the controller effects during register transfer level synthesis
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
◽
10.1109/edtc.1994.326916
◽
2002
◽
Cited By ~ 4
Author(s):
C. Ramachandran
◽
F.J. Kurdahi
Keyword(s):
Register Transfer Level
◽
Register Transfer
Download Full-text
Test pattern generators for distributed and embedded built-in self-test at register transfer level
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design
◽
10.1109/isqed.2001.915236
◽
2002
◽
Author(s):
V. Vorisek
Keyword(s):
Test Pattern
◽
Register Transfer Level
◽
Register Transfer
◽
Self Test
◽
Built In Self Test
◽
Pattern Generators
Download Full-text
A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level
10.1109/dac18074.2021.9586248
◽
2021
◽
Author(s):
Johannes Muller
◽
Mohammad Rahmani Fadiheh
◽
Anna Lena Duque Anton
◽
Thomas Eisenbarth
◽
Dominik Stoffel
◽
...
Keyword(s):
Register Transfer Level
◽
Formal Approach
◽
Register Transfer
Download Full-text
A Register Transfer Level Approach for Intermittent Semi-Concurrent Error Detection
2010 2nd International Conference on E-business and Information System Security
◽
10.1109/ebiss.2010.5473579
◽
2010
◽
Author(s):
Donghu Yang
◽
Jianhui Jiang
◽
Jie Yin
◽
Jipeng Huang
Keyword(s):
Error Detection
◽
Register Transfer Level
◽
Concurrent Error Detection
◽
Register Transfer
Download Full-text
Efficient Digital System Design Methodology with SystemC Register Transfer Level Modeling
IEEE SoutheastCon, 2004. Proceedings.
◽
10.1109/secon.2004.1287966
◽
2004
◽
Author(s):
M.C. Zabawa
◽
S.V. Wunnava
Keyword(s):
System Design
◽
Design Methodology
◽
Register Transfer Level
◽
Digital System
◽
Register Transfer
◽
Digital System Design
Download Full-text
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