Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

Test pattern generators for distributed and embedded built-in self-test at register transfer level

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915236 ◽

2002 ◽

Author(s):

V. Vorisek

Keyword(s):

Test Pattern ◽

Register Transfer Level ◽

Register Transfer ◽

Self Test ◽

Built In Self Test ◽

Pattern Generators

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Foundry's perspective of system integration: quality design and time-to-volume

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915214 ◽

2002 ◽

Author(s):

Sheldon Wu ◽

F. Wang ◽

Lie-Szu Juang

Keyword(s):

System Integration ◽

Quality Design

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Impact of on-chip inductance when transitioning from Al to Cu based technology

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915223 ◽

2002 ◽

Author(s):

T. Chen

Keyword(s):

On Chip

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A global driver sizing tool for functional crosstalk noise avoidance

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915221 ◽

2002 ◽

Cited By ~ 1

Author(s):

M.R. Becer ◽

D. Blaauw ◽

S. Sirichotiyakul ◽

R. Levy ◽

Chanhee Oh ◽

...

Keyword(s):

Crosstalk Noise

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Hot-carrier-induced circuit degradation for 0.18 μm CMOS technology

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915244 ◽

2002 ◽

Author(s):

Wei Li ◽

Qiang Li ◽

J.S. Yuan ◽

J. McConkey ◽

Yuan Chen ◽

...

Keyword(s):

Cmos Technology ◽

Hot Carrier

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Spice model quality: process development viewpoint

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915274 ◽

2002 ◽

Cited By ~ 1

Author(s):

P. Bendix

Keyword(s):

Process Development ◽

Model Quality ◽

Spice Model ◽

Quality Process

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Defect-oriented fault simulation and test generation in digital circuits

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915257 ◽

2002 ◽

Cited By ~ 4

Author(s):

W. Kuzmicz ◽

W. Pleskacz ◽

J. Raik ◽

R. Ubar

Keyword(s):

Test Generation ◽

Digital Circuits ◽

Fault Simulation

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Trading bitwidth for array size: a unified reconfigurable arithmetic processor design

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915251 ◽

2002 ◽

Author(s):

Rong Lin

Keyword(s):

Array Size ◽

Processor Design ◽

Arithmetic Processor

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Models for interconnect capacitance extraction

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915222 ◽

2002 ◽

Cited By ~ 23

Author(s):

A. Husain

Keyword(s):

Capacitance Extraction

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Constructive floorplanning with a yield objective

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915240 ◽

2002 ◽

Cited By ~ 1

Author(s):

R. Prasad ◽

I. Koren

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Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Test pattern generators for distributed and embedded built-in self-test at register transfer level

Foundry's perspective of system integration: quality design and time-to-volume

Impact of on-chip inductance when transitioning from Al to Cu based technology

A global driver sizing tool for functional crosstalk noise avoidance

Hot-carrier-induced circuit degradation for 0.18 μm CMOS technology

Spice model quality: process development viewpoint

Defect-oriented fault simulation and test generation in digital circuits

Trading bitwidth for array size: a unified reconfigurable arithmetic processor design

Models for interconnect capacitance extraction

Constructive floorplanning with a yield objective

Export Citation Format

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Test pattern generators for distributed and embedded built-in self-test at register transfer level

Foundry's perspective of system integration: quality design and time-to-volume

Impact of on-chip inductance when transitioning from Al to Cu based technology

A global driver sizing tool for functional crosstalk noise avoidance

Hot-carrier-induced circuit degradation for 0.18 μm CMOS technology

Spice model quality: process development viewpoint

Defect-oriented fault simulation and test generation in digital circuits

Trading bitwidth for array size: a unified reconfigurable arithmetic processor design

Models for interconnect capacitance extraction

Constructive floorplanning with a yield objective

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design
Latest Publications