A Novel Probability-Based Logic-Locking Technique: ProbLock

Integrated circuit (IC) piracy and overproduction are serious issues that threaten the security and integrity of a system. Logic locking is a type of hardware obfuscation technique where additional key gates are inserted into the circuit. Only the correct key can unlock the functionality of that circuit; otherwise, the system produces the wrong output. In an effort to hinder these threats on ICs, we have developed a probability-based logic-locking technique to protect the design of a circuit. Our proposed technique, called “ProbLock”, can be applied to both combinational and sequential circuits through a critical selection process. We used a filtering process to select the best location of key gates based on various constraints. Each step in the filtering process generates a subset of nodes for each constraint. We also analyzed the correlation between each constraint and adjusted the strength of the constraints before inserting key gates. We tested our algorithm on 40 benchmarks from the ISCAS ’85 and ISCAS ’89 suites. We evaluated ProbLock against a SAT attack and measured how long the attack took to successfully generate a key value. The SAT attack took longer for most benchmarks using ProbLock which proves viable security in hardware obfuscation.

Digital Building Blocks using Perceptrons in Neural Networks

Most microprocessors and microcontrollers are based on Digital Electronics building Blocks. Digital Electronics gives us a number of combinational and sequential circuits for various arithmetic and logical operations. These include Adders, Subtracters, Encoders, Decoders, Multiplexers, DE multiplexers and Flip Flops. These further combine into higher configurations to perform advanced operations. These operations are done using logic circuits in digital electronics. But in this paper, we explore the human reasoning approach using artificial neural networks. We will look into neural implementations of logic gates implemented with SLP (Single layer perceptron) and MLP (Multi-Layer Perceptron). We will also look into recurrent neural architectures to make basic memory elements, viz. Flip Flops which use feedback and may involve in one or more neuron layers.

Design of One-Bit Magnitude Comparator using Photonic Crystals

At present, photonic crystals (PhCs) are used to design various combinational and sequential circuits. In this paper, an all-optical one-bit magnitude comparator is proposed using PhC waveguide without using nonlinear material. It is based on beam interference principle, using T-shaped lattice with silicon dielectric rods in air background. It is demonstrated through finite-difference time-domain simulation and verified numerically using MATLAB simulation. The size of PhC lattice structure can be as small as 19.167a×19.167a, where ‘a’ is the lattice constant of the PhC.

Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

In today's electronic sector, low energy has appeared as a major feature. Power effectiveness is one of the most significant characteristics of contemporary, high-speed and mobile digital devices. Different methods are available to decrease energy dissipation at distinct stages of the planning method and have been applied. As the transistors count per device region continues to rise, while the switching energy does not rise at the same pace, power dissipation increases, and heat removal becomes more hard and costly. The power consumption of electronic appliances can be decreased by using various logic types. For such low-power electronic applications, adiabatic logic mode is very appealing. Using adiabatic logic, distinct powerefficient gates are intended in this document and contrasted for energy dissipation, propagation delay and no of the transistors used. In addition, the circuit developer can use these gates in the combinational and sequential circuits to develop low-power systems. The simulations of these gates are carried out in 90 nm technology using cadence virtuoso instrument.

Metodología para programar procesos con relevadores inteligentes

Objective: Design of a methodology based on problem based learning, to program intelligent relays and solve process automation problems. Methodology that will allow students and engineers interested in acquiring theoretical, heuristic and axiological skills on intelligent relay programming. The methodology will allow to acquire the proposed competences and process automation problems can be solved. Contribution: The methodology is designed with solved exercises in electrical, civil and mechanical engineering, which allow us to visualize the importance of learning to program processes with intelligent relays. The methodology helps the programmer acquire a critical thinking considering aspects such as the environment, integral health and safety. There is transversality to relate Educational programs of different disciplines and enrich the knowledge of intelligent relays from the programming and interpretation of block diagrams, ladder diagrams and time diagrams, familiarize yourself with the use of technical language and digital language (combinational and sequential circuits Follow the safety instructions and parameters to be manipulated for the correct operation of the electrical and electronic devices and establish the operation of the process.

All-Optical Half-Adder Circuit Based on Beam Interference Principle of Photonic Crystal

Now a day’s photonic crystals (PhCs) are in trends for designing of various integrated circuits like combinational and sequential circuits. The designing of all-optical half adder circuit based on beam interference principle, using T-shaped square lattice with silica dielectric rods in air background, is proposed. This design is a combination of two structures: one part of it works as AND gate and other part works as XOR gate. This structure is simulated using finite difference time domain (FDTD) method and verified numerically using PWE band solver and also using MATLAB.