In this chapter we discuss techniques to design and implement multirate digital filters with low power consumption which also allow a reduction in the design effort, since the resulting circuits are highly modular and regular and can relatively easily be incorporated in the normal design flow of commercial tools. First we briefly review techniques that can be applied at various design levels, i.e., from algorithm level down to layout, to reduce the power consumption in CMOS implementations of both digital FIR and IIR filters and are useful in many other DSP algorithms. Second, we discuss the properties of lattice wave digital filters and various techniques to design efficient multirate digital filters for changing the sampling rate by a factor of two. Third, we discuss the design of multistage multirate digital FIR filter structures for arbitrary bandwidths. Finally, we provide some design examples.
VLSI Implementation of Fixed-Point Lattice Wave Digital Filters for Increased Sampling Rate
